RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 47

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

11.4
11.5
11.5.1
Datasheet
Program Resume
To resume (i.e., continue) a program suspend operation, execute the Program Resume command.
The Resume command can be written to any device address. When a program operation is nested
within an erase suspend operation and the Program Suspend command is issued, the device will
suspend the program operation. When the Resume command is issued, the device will resume and
complete the program operation. Once the nested program operation is completed, an additional
Resume command is required to complete the block erase operation. The device supports a
maximum suspend/resume of two nested routines. See
Flowchart” on page
Buffered Enhanced Factory Programming (Buffered-EFP)
Buffered-EFP speeds up MLC flash programming for today’s beat-rate-sensitive manufacturing
environments. This enhanced algorithm eliminates traditional elements that drive up overhead in
off-board or on-board, off-line or in-line, manual or automated programmer systems. Buffered-EFP
is different than non-buffered EFP mode; it incorporates a write buffer to spread MLC program
performance across 32 data words. Additionally, verification occurs in the same phase as
programming, an inherent requirement of two-bit-per-cell technology to accurately program the
correct state.
A single two-cycle command sequence programs an entire block of data. This enhancement
eliminates three write cycles per buffer page, two commands and the word count per each set of 32
data words. Host programmer bus cycles fill the device write buffer, followed by a status check of
SR.0 to determine when the data from that page has completed programming into sequential flash
memory locations. Following the buffer-to-flash programming sequence, the WSM increments
internal addressing to automatically select the next 32-word array boundary. This aspect of
Buffered-EFP saves programming equipment address-bus setup overhead. In combination, these
enhancements allow programming equipment to stream data to the device.
With proper continuity testing, programming equipment can rely on the WSM internal verification
to assure the device has programmed properly. This capability eliminates the external post-program
verification and its associated overhead. Buffered-EFP consists of three phases: setup, program/
verify, and exit. Refer to
Flowchart” on page 73
Buffered-EFP Requirements and Considerations
Buffered-EFP requirements:
•
•
•
•
•
•
Ambient temperature: T
V
V
Target block unlocked before issuing the Setup and Confirm commands
WA
through all data streaming in the target block, until transition to the exit phase is desired
WA
CC
PEN
0
0
within specified operating range
(first word address in block to be programmed) must be held constant from setup phase
must align with the start of an array buffer boundary
driven to V
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
72.
PENH
for a graphical representation of Buffered-EFP.
Figure 28, “Buffered Enhanced Factory Programming Procedure
A
= 25 °C ±5 °C
Figure 27, “Program Suspend/Resume
1
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