RC28F256K3C120 NUMONYX, RC28F256K3C120 Datasheet - Page 55

• Manufacturer Part Number: RC28F256K3C120
• Description: IC FLASH 256MBIT 120NS 64BGA
• Manufacturer: NUMONYX

Specifications of RC28F256K3C120

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 256M (16Mx16)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 853157

13.2.1
13.2.2
13.2.3
13.3
Datasheet
Reading the Protection Registers
To read Protection Register data, issue the Read Identifier command along with the address
corresponding to the desired word of register data. (See
data is read 16 bits at a time.
Programming the Protection Registers
To program a Protection Register, issue the Protection Program command, plus a desired
Protection Register offset. See
Protection Register. Only one word may be programmed to the user segment at a time. Issuing the
Protection Program command outside the register’s address space results in a status register error
(SR4=1).
Locking the Protection Registers
To lock a Protection Register, program the corresponding bit in the PR Lock Register by issuing the
Program PR Lock Register command followed by the desired PR Lock Register data.
Bit 0 of PR Lock Register 0 is already programmed at the Intel factory and locks PR0[63:0]. Bit 1
of PR Lock Register 0 can be programmed by the user to lock the user-programmable portion of
Protection Register 0, namely PR0[128:64]. The rest of the bits in PR Lock Register 0 are not used.
PR Lock Register 1 controls the locking of the remaining 128-bit Protection Registers. Each of the
16 bits of PR Lock Register 1 corresponds to one of the 16 128-bit Protection Registers. For
example, to lock PR6, program bit 5 in PR Lock Register 1.
After PR Lock Register bit 1 is programmed (locked), the user segment of the Protection Register
cannot be changed. Protection Program commands written to a locked section result in a status
register error (SR[5:4]=0b11).
Array Protection
The V
below the V
operation, V
operation, poll the status register and analyze the bits.
PEN
signal is a hardware mechanism to prohibit array alteration. When the V
PENLK
PEN
must be set to a valid voltage level. To determine the status of an erase or program
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
voltage, array contents cannot be altered. To ensure a proper erase or program
Figure 24 on page 54
for appropriate address offsets of the
Figure 24 on page
54.) Protection Register
PEN
voltage is
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