PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 45

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

PSD4235G2
9.3
since the Toggle Flag bit (DQ6/DQ14) may have changed simultaneously with the Error Flag
bit (DQ5/DQ13, see
The Error Flag bit (DQ5/DQ13) is set if either an internal timeout occurred while the
embedded algorithm attempted to program, or if the MCU attempted to program a ’1’ to a bit
that was not erased (not erased is logic 0).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the word that was written to Flash
memory with the word that was intended to be written.
When using the Data Toggle method after an Erase cycle,
Flag bit (DQ6/DQ14) toggles until the Erase cycle is complete. A '1' on the Error Flag bit
(DQ5/DQ13) indicates a timeout condition on the Erase cycle, a ’0’ indicates no error. The
MCU can read any even location within the sector being erased to get the Toggle Flag bit
(DQ6/DQ14) and the Error Flag bit (DQ5/DQ13).
PSDsoft Express generates ANSI C code functions which implement these Data Toggling
algorithms.
Unlock Bypass
The Unlock Bypass instruction allows the system to program words to the Flash memories
faster than using the standard Program instruction. The Unlock Bypass mode is entered by
first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the
Unlock Bypass command, 20h (as shown in
Unlock Bypass mode.
A two-cycle Unlock Bypass Program instruction is all that is required to program in this
mode. The first cycle in this instruction contains the Unlock Bypass Program command,
A0h. The second cycle contains the program address and data. Additional data is
programmed in the same manner. This mode dispense with the initial two Unlock cycles
required in the standard Program instruction, resulting in faster total programming time.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
instructions are valid.
To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset
instruction. The first cycle must contain the data 90h; the second cycle the data 00h.
Addresses are Don’t Care for both cycles. The Flash memory then returns to READ mode.
Figure
6).
Table
29). The Flash memory then enters the
Figure 6
Programming Flash memory
still applies. the Toggle
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