PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 84

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

I/O ports
Table 41.
1. N/A = Not Applicable.
20.6
20.7
20.8
84/129
80C51XA
All other MCU with
multiplexed bus
MCU
I/O port latched address output assignments
Address In mode
For MCUs that have more than 16 address signals, the higher addresses can be connected
to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be
latched in the input macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is
included in the DPLD equations for the primary Flash memory, secondary Flash memory or
SRAM is considered to be an address input.
Data Port mode
Ports F and G can be used as a data bus port for a MCU with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O
functions are disabled in Ports F and G if the ports are configured as a Data Port. Data Port
mode is automatically configured in PSDsoft Express when a non-multiplexed bus MCU is
selected.
Peripheral I/O mode
Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all
of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is
enabled by setting bit 7 of the VM register to a '1.'
directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for
PSEL0 and/or PSEL1 must be specified in PSDsoft Express. The buffer is tri-stated when
PSEL0 or PSEL1 is not active.
(PE3-PE0)
Address
Port E
a3-a0
N/A
(PE7-PE4)
Address
Address
Port E
a7-a4
a7-a4
(PF3-PF0)
Address
Port F
a3-a0
N/A
(1)
Figure 27
(PF7-PF4)
Address
Address
Port F
a7-a4
a7-a4
shows how Port A acts as a bi-
(PG3-PG0)
Address
Address
a11-a8
a11-a8
Port G
PSD4235G2
(PG7-PG4)
Address
a15-a12
Address
a15-a12
Port G