PSD4235G2V-12UI STMicroelectronics, PSD4235G2V-12UI Datasheet - Page 49

• Manufacturer Part Number: PSD4235G2V-12UI
• Description: IC FLASH 4MBIT 120NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2V-12UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Number Of Macrocells: 24
• Maximum Operating Frequency: 25.6 MHz
• Delay Time: 90 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1970

PSD4235G2
11
11.1
11.2
11.3
Specific features
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash memory can be separately protected against
Program and Erase cycles. Sector Protection provides additional data security because it
disables all Program or Erase cycles. This mode can be activated (or deactivated) through
the JTAG-ISP Port or a device programmer.
Sector protection can be selected for each sector using the PSDsoft Express program. This
automatically protects selected sectors when the device is programmed through the JTAG
Port or a device programmer. Flash memory sectors can be unprotected to allow updating of
their contents using the JTAG Port or a device programmer. The MCU can read (but cannot
change) the sector protection bits.
Any attempt to program or erase a protected Flash memory sector is ignored by the device.
The Verify operation results in a READ of the protected data. This allows a guarantee of the
retention of the Protection status.
The sector protection status can be read by the MCU through the Flash memory protection
and Secondary Flash memory protection registers (in the CSIOP block) or use the Read
Sector Protection instruction. See
Reset
The Reset instruction consists of one WRITE cycle (see
preceded by the standard two WRITE decoding cycles (writing AAh to AAAh, and 55h to
554h).
The Reset instruction must be executed after:
●
●
The Reset instruction immediately puts the Flash memory back into normal READ mode.
However, if there is an error condition (with the Error Flag bit (DQ5/DQ13) set to ’1’) the
Flash memory will return to the READ mode in 25 μs after the Reset instruction is issued.
The Reset instruction is ignored when it is issued during a Program or Bulk Erase cycle of
the Flash memory. The Reset instruction aborts any on-going Sector Erase cycle, and
returns the Flash memory to the normal READ mode in 25 μs.
Reset (RESET) pin
A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash
memory to the READ mode. When the reset occurs during a Program or Erase cycle, the
Flash memory takes up to 25 μs to return to the READ mode. It is recommended that the
Reset (RESET) pulse (except for Power-on Reset, as described in
25μs so that the Flash memory is always ready for the MCU to fetch the bootstrap
instructions after the Reset cycle is complete.
Reading the Flash Protection Status or Flash ID
An Error condition has occurred (and the device has set the Error Flag bit (DQ5/DQ13)
to ’1’) during a Flash memory Program or Erase cycle.
Table 19
to
Table
20.
Table
29). It can also be optionally
Section
Specific features
22.1) be at least
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