PSD813F1A-90UI STMicroelectronics, PSD813F1A-90UI Datasheet - Page 17

• Manufacturer Part Number: PSD813F1A-90UI
• Description: IC FLASH 1MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1980

PSD REGISTER DESCRIPTION AND ADDRESS OFFSET
Table
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 5. I/O Port Latched Address Output Assignments
Note: 1. See the section entitled
Table 6. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
8051XA (8-bit)
80C251 (page mode)
All other 8-bit multiplexed
8-bit non-multiplexed bus
Data In
Control
Data Out
Direction
Drive Select
Input Macrocell
Enable Out
Output Macrocells
AB
Output Macrocells
BC
Mask Macrocells
AB
Mask Macrocells
BC
Primary Flash
Protection
Secondary Flash
memory
Protection
JTAG Enable
PMMR0
PMMR2
Page
VM
Register Name
2. N/A = Not Applicable
5
shows the offset addresses to the PSD
MCU
(1)
Port
0C
0A
00
02
04
06
08
20
22
A
I/O PORTS, page
Port
0D
0B
01
03
05
07
09
20
21
22
23
B
N/A
N/A
Address a3-a0
N/A
Port A (3:0)
Port
1A
10
12
14
16
18
21
23
C
52, on how to enable the Latched Address Output function.
Port
1B
11
13
15
17
D
Port A
Other
Address a7-a4
N/A
Address a7-a4
N/A
(2)
C0
C2
C7
B0
B4
E0
E2
Port A (7:4)
(1)
Table
in CSIOP space. The following section gives a
more detailed description.
Reads Port pin as input, MCU I/O input mode
Selects mode between MCU I/O or Address Out
Stores data for output to Port pins, MCU I/O output
mode
Configures Port pin as input or output
Configures Port pins as either CMOS or Open Drain
on some pins, while selecting high slew rate on other
pins.
Reads Input Macrocells
Reads the status of the output enable to the I/O Port
driver
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Blocks writing to the Output Macrocells AB
Blocks writing to the Output Macrocells BC
Read only – Flash Sector Protection
Read only – PSD Security and EEPROM Sector
Protection
Enables JTAG Port
Power Management Register 0
Power Management Register 2
Page Register
Places PSD memory areas in Program and/or Data
space on an individual basis.
6
provides brief descriptions of the registers
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (3:0)
Description
Port B
N/A
Address a15-a12
Address a7-a4
Address a7-a4
(2)
Port B (7:4)
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