PSD813F1A-90UI STMicroelectronics, PSD813F1A-90UI Datasheet - Page 58

• Manufacturer Part Number: PSD813F1A-90UI
• Description: IC FLASH 1MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1980

PSD813F1A
Direction Register
The Direction Register, in conjunction with the out-
put enable (except for Port D), controls the direc-
tion of data flow in the I/O Ports. Any bit set to ‘1’
in the Direction Register will cause the corre-
sponding pin to be an output, and any bit set to ‘0’
will cause it to be an input. The default mode for all
port pins is input.
Figure 29., page 60
the Port Architecture diagrams for Ports A/B and
C, respectively. The direction of data flow for Ports
A, B, and C are controlled not only by the direction
register, but also by the output enable product
term from the PLD AND array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 25. Since
Port D only contains three pins (shown in
32., page
has only the three least significant bits active.
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS for some port pins, and
controls the slew rate for the other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
‘1.’ The default pin drive is CMOS.
Aside: the slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
Table 26. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
58/111
Port A
Port B
Port C
Port D
Register
Drive
63), the Direction Register for Port D
Open
Drain
Open
Drain
Open
Drain
NA
Bit 7
1
and
Open
Drain
Open
Drain
Open
Drain
NA
Figure 30., page 61
1
Bit 6
Open
Drain
Open
Drain
Open
Drain
NA
Bit 5
1
Figure
show
Open
Drain
Open
Drain
Open
Drain
NA
1
Bit 4
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to ‘1.’ The default rate is slow slew.
Table
C, and D. It summarizes which pins can be config-
ured as Open Drain outputs and which pins the
slew rate can be set for.
Table 23. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 24. Port Pin Direction Control, Output
Enable P.T. Defined
Table 25. Port Direction Assignment Example
0
1
0
0
1
1
0
Bit 7
Direction Register Bit
Register Bit
Direction
Slew
Rate
Slew
Rate
Open
Drain
NA
26
0
Bit 3
1
Bit 6
shows the Drive Register for Ports A, B,
0
Bit 5
Slew
Rate
Slew
Rate
Open
Drain
Slew
Rate
0
1
0
1
Output Enable
Bit 2
0
Bit 4
P.T.
Input
Output
0
Bit 3
Slew
Rate
Slew
Rate
Open
Drain
Slew
Rate
Bit 1
Port Pin Mode
1
Bit 2
Input
Output
Output
Output
Port Pin Mode
1
Bit 1
Slew
Rate
Slew
Rate
Open
Drain
Slew
Rate
Bit 0
1
Bit 0