PSD813F1A-90UI STMicroelectronics, PSD813F1A-90UI Datasheet - Page 37

• Manufacturer Part Number: PSD813F1A-90UI
• Description: IC FLASH 1MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1980

COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate 3 external chip selects,
routed to Port D.
Although external chip selects can be produced by
any Output Macrocell, these three external chip
selects on Port D do not consume any Output
macrocells.
As shown in
the following blocks:
■
■
■
■
Figure 17. Macrocell and I/O Port
24 Input macrocells (IMCs)
16 Output macrocells (OMCs)
Macrocell Allocator
Product Term Allocator
Figure 15., page
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT
CLOCK
CLOCK
SELECT
PT CLEAR
GLOBAL
CLOCK
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
MACROCELL FEEDBACK
PT OUTPUT ENABLE ( OE )
I/O PORT INPUT
PT PRESET
35, the CPLD has
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
MCU LOAD
Q
MCU ADDRESS / DATA BUS
SELECT
COMB.
/REG
MACROCELL
CONTROL
OUT TO
LOAD
DATA
MACROCELL
MCU
I/O PORT
ALLOC.
TO
■
■
Each of the blocks are described in the subsec-
tions that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the microcon-
troller. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND logic array as required in
most standard PLD macrocell architectures.
OUTPUT
CPLD
AND array capable of generating up to 137
product terms
Four I/O ports.
ALE/AS
DATA
CPLD OUTPUT
ADDRESS OUT
I/O PORTS
WR
WR
INPUT MACROCELLS
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
PSD813F1A
I/O PIN
AI02874
37/111