M25P40-VMN6P NUMONYX, M25P40-VMN6P Datasheet - Page 18

• Manufacturer Part Number: M25P40-VMN6P
• Description: IC FLASH 4MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P40-VMN6P

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 512K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 3.6V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3598; 497-3598

6
Note:
Table 4.
18/59
FAST_READ
Instruction
WREN
WRSR
RDSR
READ
WRDI
RDID
RES
DP
PP
SE
BE
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip
Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data input (D), each bit being latched on the rising
edges of Serial Clock (C). The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(FAST_READ), Read Status Register (RDSR), Read Identification (RDID) or Release from
Deep Power-down, and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High
after any bit of the data-out sequence is being shifted out.
For a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable (WRDI), or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary. Otherwise the
instruction is rejected and not executed. That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Output Hi-Z is defined as the point where data out is no longer driven.
Instruction set
Write Enable
Write Disable
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
Read Data Bytes at Higher Speed
Page Program
Sector Erase
Bulk Erase
Deep Power-down
Release from Deep Power-down,
and Read Electronic Signature
Release from Deep Power-down
Description
One-byte instruction
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1011 1001
1010 1011
1001 1111
1100 0111
code
ABh
0Bh
D8h
C7h
B9h
06h
04h
9Fh
05h
01h
03h
02h
Table 4: Instruction
Address
bytes
0
0
0
0
0
3
3
3
3
0
0
0
0
Dummy
bytes
0
0
0
0
0
0
1
0
0
0
0
3
0
set.
1 to 256
1 to 20
bytes
1 to ∞
1 to ∞
1 to ∞
1 to ∞
Data
0
0
1
0
0
0
0