CY62167DV30LL-45ZXIT Cypress Semiconductor Corp, CY62167DV30LL-45ZXIT Datasheet - Page 5

• Manufacturer Part Number: CY62167DV30LL-45ZXIT
• Description: IC SRAM 16MBIT 45NS 48TSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62167DV30LL-45ZXIT

• Format - Memory: RAM
• Memory Type: SRAM
• Memory Size: 16M (1M x 16)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP I
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05328 Rev. *G
Data Retention Waveform
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
15. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V
16. At any given temperature and voltage condition, t
17. t
18. The internal Write time of the memory is defined by the overlap of WE, CE
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
of 0 to V
given device.
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
CE
BHE
HZOE
Parameter
1
CE
V
, t
,
or
BLE
HZCE
CC
or
CC(typ.)
2
, t
[18]
HZBE
, and output loading of the specified I
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to LOW Z
OE HIGH to High Z
CE
CE
CE
CE
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write Cycle Time
CE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
HZWE
1
1
1
1
1
1
HIGH and CE
HIGH and CE
LOW and CE
LOW and CE
LOW and CE
LOW and CE
transitions are measured when the outputs enter a high impedance state.
[14]
Description
Over the Operating Range
2
2
2
2
2
2
[16]
[16, 17]
[16, 17]
[16]
HIGH to Data Valid
HIGH to Low Z
LOW to High Z
HIGH to Power-up
LOW to Power-down
HIGH to Write End
V
HZCE
t
CC
CDR
OL
, min.
[16]
is less than t
/I
[16, 17]
OH
as shown in the “AC Test Loads and Waveforms” section.
[16, 17]
[16]
LZCE
, t
DATA RETENTION MODE
HZBE
1
[15]
= V
Min.
45
10
10
10
45
40
40
35
40
25
10
IL
is less than t
5
0
0
0
0
45 ns
, BHE and/or BLE = V
V
DR
> 1.5 V
[12]
Max.
45
45
25
15
20
45
45
15
15
LZBE
, t
HZOE
Min.
55
10
10
10
55
40
40
40
40
25
10
IL
5
0
0
0
0
is less than t
, and CE
55 ns
CY62167DV30 MoBL
Max.
2
55
55
25
20
20
55
55
20
20
= V
LZOE
IH
V
. All signals must be ACTIVE to initiate
CC
, and t
t
R
Min.
, min.
70
10
10
10
70
60
60
45
60
30
10
5
0
0
0
0
HZWE
70 ns
CC(typ)
is less than t
Max.
70
70
35
25
25
70
25
25
70
/2, input pulse levels
Page 5 of 12
LZWE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for any
®