CY7C1339G-133AXE Cypress Semiconductor Corp, CY7C1339G-133AXE Datasheet - Page 3

• Manufacturer Part Number: CY7C1339G-133AXE
• Description: IC SRAM 4MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339G-133AXE

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05520 Rev. *F
Pin Configurations
Pin Definitions
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
0
, A
Name
1
2
3
A
C
, BW
, BW
1
, A
B
D
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
I/O
(continued)
M
A
B
C
D
E
G
H
K
N
P
R
U
F
J
L
T
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
are fed to the two-bit counter. .
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
loaded. Not connected for BGA. Where referenced, CE
document for BGA.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
NC/288M
NC/144M
2
1
1
and CE
and CE
and CE
V
V
V
V
V
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
DDQ
DDQ
DDQ
DDQ
DDQ
1
C
C
C
C
D
D
D
D
2
3
3
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device. CE
NC/72M
to select/deselect the device.CE
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CE
V
NC
NC
NC
A
A
A
2
DD
2
C
C
C
C
D
D
D
D
119-Ball BGA Pinout
MODE
BW
BW
V
V
V
V
V
V
V
V
NC
NC
A
A
A
A
3
SS
SS
SS
SS
SS
SS
SS
SS
D
c
ADSC
ADSP
BWE
ADV
CLK
V
CE
V
V
GW
NC
OE
NC
NC
A1
A0
A
4
DD
DD
DD
1
Description
2
3
BW
BW
is sampled only when a new external address is
is sampled only when a new external address is
V
V
V
V
V
V
V
V
NC
NC
NC
A
A
A
A
5
SS
SS
SS
SS
SS
SS
SS
SS
A
B
1
, CE
3
NC/36M
NC/9M
is assumed active throughout this
2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
, and CE
V
NC
NC
NC
A
A
A
6
DD
B
B
B
B
A
A
A
A
1
NC/576M
is HIGH. CE
3
NC/1G
V
V
V
V
V
are sampled active. A1, A0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
ZZ
DDQ
DDQ
DDQ
DDQ
DDQ
7
B
B
B
B
A
A
A
A
[A:D]
CY7C1339G
and BWE).
1
is sampled only
Page 3 of 18
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