CY7C1339G-133AXE Cypress Semiconductor Corp, CY7C1339G-133AXE Datasheet - Page 6

• Manufacturer Part Number: CY7C1339G-133AXE
• Description: IC SRAM 4MBIT 133MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339G-133AXE

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-05520 Rev. *F
Truth Table
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Deselect Cycle, Power-down
Snooze Mode, Power-down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BW
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
(BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
1
, CE
A
, BW
Operation
2
, and CE
B
, BW
[2, 3, 4, 5, 6, 7]
C
, BW
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
D
), BWE, GW = H.
Add. Used CE
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
None
Next
Next
Next
Next
Next
Next
H
H
H
H
H
H
H
L
L
L
L
X
L
L
L
L
L
X
X
X
X
X
X
1
CE
X
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
2
A
, BW
CE
H
H
X
X
X
X
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
L
B
, BW
3
ZZ
C
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
, BW
D
ADSP
) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
X
H
H
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
ADSC
H
H
H
H
H
H
H
H
X
X
X
X
X
H
H
H
H
L
L
L
L
L
L
1
and CE
ADV WRITE OE CLK
[A: D]
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
L
L
L
L
L
L
2
. Writes may occur only on subsequent clocks
.
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
CY7C1339G
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
X
Page 6 of 18
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
Tri-State
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
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