W19B320BTT7H Winbond Electronics, W19B320BTT7H Datasheet - Page 15

• Manufacturer Part Number: W19B320BTT7H
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: Winbond Electronics

Specifications of W19B320BTT7H

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: W19B320BTT-H; W19B320BTT-H

Enter Security Sector command sequence. The device continues to access the Security Sector region
until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security
Sector command sequence returns the device to normal operation. See “Security Sector Flash
Memory Region” for further information.
6.2.4
The device can be programmed either by word or byte, which depending on the state of the #BYTE
pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by
writing two unlock write cycles, followed by the program setup command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The device automatically
provides internally generated program pulses and verifies the programmed cell margin.
Once the Embedded Program algorithm is complete, the bank then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please
note that a hardware reset will immediately stop the program operation. The program command
sequence should be reinitiated when the bank has returned to the read mode, in order to ensure data
integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6
status bits to indicate that the operation is successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can change “0” to “1.”
6.2.5
The unlock bypass feature provides the system to program bytes or words to a bank which is faster
than using the standard program command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass
command, 20h, is followed. Then, the bank enters into the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. In the same manner, additional data is programmed. This mode dispenses
with the initial two unlock cycles which required in the standard program command sequence,
resulting in faster total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence
to exit the unlock bypass mode. The first cycle must contain the bank address and the data 90h. The
second cycle needs to contain the data 00h. Then, the bank returns to the read mode.
The device offers accelerated program operations by the #WP/ACC pin. When the V
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
V
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
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in any operation other than accelerated programming; otherwise the device may be damaged. In
Byte/Word Program Command Sequence
Unlock Bypass Command Sequence
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W19B320BT/B DATASHEET
Publication Release Date:Dec. 25, 2007
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is set at the
Revisionv A3