W19B320BTT7H Winbond Electronics, W19B320BTT7H Datasheet - Page 18

• Manufacturer Part Number: W19B320BTT7H
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: Winbond Electronics

Specifications of W19B320BTT7H

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: W19B320BTT-H; W19B320BTT-H

address falls within a protected sector, #Data Polling on DQ7 is active for about 1μs, and then that
bank returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded
Erase algorithm has completed, or when the bank enters the Erase Suspend mode, #Data Polling
produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to
read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100 μs, and then the bank returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address
within a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the
DQ7 output, the system may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still
invalid. Valid data on DQ0-DQ7 will appear on successive read cycles.
6.3.2
The
progress or complete. The
command sequence. Since
parallel with a pull-up resistor to V
When the output is low (Busy), the device is actively erasing or programming. (This includes programming
in the Erase Suspend mode.) When the output is high (Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-suspend-read mode.
6.3.3
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any
address, and is valid after the rising edge of the final
program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either
completed, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100 μs, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress),
DQ6 toggles. While if the device enters the Erase Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively,
the system can use DQ7 (see DQ7: #Data Polling).
RY/#BY
RY/#BY: Ready/#Busy
DQ6: Toggle Bit I
is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in
RY/#BY
RY/#BY
DD
.
is an open-drain output, several
status is valid after the rising edge of the final
#OE
or
#CE
- 18 -
W19B320BT/B DATASHEET
#WE
to control the read cycles. Once the operation has
pulse in the command sequence (before the
Publication Release Date:Dec.25, 2007
RY/#BY
pins can be tied together in
#WE
pulse in the
Revisionv A3