NAND01GR3B2BZA6E NUMONYX, NAND01GR3B2BZA6E Datasheet - Page 46

• Manufacturer Part Number: NAND01GR3B2BZA6E
• Description: IC FLASH 1GBIT 63VFBGA
• Manufacturer: NUMONYX

Specifications of NAND01GR3B2BZA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 1G (128M x 8)
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 63-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

DC and AC parameters
Table 25.
1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See
2.
3. During a program/erase enable operation, t
4. ES = electronic signature.
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Symbol
t
t
t
t
t
t
t
t
t
t
t
ALLRL1
ALLRL2
t
t
t
t
t
t
t
t
t
WHWH
t
t
t
t
BLBH1
BLBH2
BLBH3
BLBH4
BLBH5
t
CLLRL
VHWH
WHBH
EHQX
RHQX
WHBL
WHRL
EHQZ
RHQZ
VLWH
RHRL
RLRH
RLQV
BHRL
DZRL
ELQV
RLRL
Figure
During a program/erase disable Operation, t
t
WHWH
33.
is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
symbol
t
t
t
t
t
ADL
t
PROG
t
t
WW
t
t
t
BERS
t
CBSY
t
T
Alt.
t
WHR
AC characteristics for operations
t
t
RST
CLR
CHZ
RHZ
CEA
REH
t
t
REA
t
WB
RR
RC
t
AR
RP
IR
OH
R
(2)
(3)
Address Latch Low to
Read Enable Low
Ready/Busy High to Read Enable Low
Ready/Busy Low to
Ready/Busy High
Command Latch Low to Read Enable Low
Data Hi-Z to Read Enable Low
Chip Enable High to Output Hi-Z
Read Enable High to Output Hi-Z
Last address latched to data loading time during program
operations
Write protection time
Chip Enable Low to Output Valid
Read Enable High to
Read Enable Low
Chip Enable High or Read Enable high to Output Hold
Read Enable Low to
Read Enable High
Read Enable Low to
Read Enable Low
Read Enable Low to
Output Valid
Write Enable High to
Ready/Busy High
Write Enable High to Ready/Busy Low
Write Enable High to Read Enable Low
WW
WW
Read electronic signature
Read cycle
Read busy time
Program busy time
Erase busy time
Reset busy time, during ready
Reset busy time, during read
Reset busy time, during program
Reset busy time, during erase
Cache busy time
Read Enable High hold time
Read Enable pulse width
Read cycle time
Read Enable access time
Read ES access time
Read Busy time
is the delay from WP high to W High.
is the delay from WP Low to W High.
Parameter
(1)
(4)
NAND01G-B2B, NAND02G-B2C
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Typ
Min
Min
Min
Min
Min
Min
Min
Min
Min
Figure
devices
1.8 V
700
500
700
100
100
100
10
10
20
25
10
10
30
30
45
15
10
25
50
30
25
60
3
5
5
3
0
31,
Figure 32
devices
700
500
700
100
100
100
3 V
10
10
20
25
10
10
30
30
25
10
10
15
30
20
25
60
3
5
5
3
0
and
Unit
ms
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns