IDT71P71804S200BQG8 IDT, Integrated Device Technology Inc, IDT71P71804S200BQG8 Datasheet
IDT71P71804S200BQG8
Specifications of IDT71P71804S200BQG8
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IDT71P71804S200BQG8 Summary of contents
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... The DDRII SRAM has two sets of input clocks, namely the K, K clocks and the C, C clocks. In addition, the DDRII has an output “echo” clock, CQ, CQ. (Note 1) WRITE DRIVER (Note2) (Note1) 18M MEMORY ARRAY SELECT OUTPUT CONTROL 1 IDT71P71804 IDT71P71604 TM Burst of two SRAMs are high-speed synchro- ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals (LD, R/W ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Definitions Symbol Pin Function Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Definitions continued Symbol Pin Function DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Configuration IDT71P71804 ( ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Pin Configuration IDT71P71604 (512K ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Write Descriptions (1,2,3) BW Signal 0 Write Byte 0 L Write Byte 1 X Write Byte 2 X Write Byte 3 X NOTES: 1) ...
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... IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Application Example R Data Bus Address MEMORY CONTROLLER Return CLK V t Source CLK Return Source R=50 SRAM #1 W R=250 REF 6.42 8 Commercial Temperature Range SRAM #4 R=250 R 6112 drw ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Absolute Maximum Ratings Symbol Rating Supply Voltage on V with DD V TERM Respect to GND Supply Voltage on V with DDQ V TERM ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Input Leakage Current I IL Output Leakage Current I OL Operating ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range PARAMETER SYMBOL Input High Voltage (DC Input Low Voltage, ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Test Conditions (1) Parameter Symbol Core Power Supply Voltage V DD I/O Power Supply Voltage V DDQ Input High Level V IH Input ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Symbol Parameter Clock Parameters t Clock Cycle Time (K,K,C,C) KHKH t Clock Phase Jitter (K,K,C,C) KC var t Clock High Time ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Timing Waveform of Combined Read and Write Cycles NOP Read A0 Read A1 (burst of 2) (burst tKHKL ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Scan Register Definition Part Instrustion Register 512K x36 3 bits 1Mx18 3 bits Identification Register Definitions INSTRUCTION FIELD ALL DEVICES Revision Number (31:29) Device ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Boundary Scan Exit Order (1M x 18-Bit) ORDER PIN ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Boundary Scan Exit Order (512K x 36-Bit) ORDER PIN ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 JTAG DC Operating Conditions Parameter Symbol I/O Power Supply V DDQ Power Supply Voltage V DD Input High Level V IH Input Low Level ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 JTAG AC Characteristics Parameter Symbol TCK Cycle Time t CHCH TCK High Pulse Width t CHCL TCK Low Pulse Width t CLCH TMS Input ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Package Diagram Outline for 165-Ball Fine Pitch Grid Array Commercial Temperature Range 6.42 21 ...
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IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Ordering Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 “QDR SRAMs and Quad Data Rate RAMs comprise a new family ...
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IDT71P71804 ( -Bit) 71P71604 (512K x 36-Bit DDR II SRAM Burst of 2 Revision History REVISION DATE 0 07/29/05 A 04/21/06 B 10/13/08 C 04/01/09 PAGES DESCRIPTION 1-24 Released Final datasheet 1-3,7,8,10,13, Removed 2Mx8 (71P71204) ...