RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 35

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

9.0
9.1
9.1.1
Datasheet
Synch Array Read
Asynch. Reads and
Synch. Status,
Query and Identifier
Reads
Output Disable
Standby
Reset
CUI Command
Write
Array Writes
NOTES:
1. OE# and WE# should never be asserted simultaneously, but if done, OE# overrides WE#.
2. Refer to DC Characteristics. When V
3. X should be V
4. Array writes are either program or erase operations.
Table 14. Bus Operations
Mode
Bus Operations
This section provides an overview of device bus operations. The on-chip Write State Machine
(WSM) manages all block-erase and word-program algorithms. The system CPU provides control
of all in-system read, write, and erase operations of the device via the system bus.
Device commands are written to the Command User Interface (CUI) to control all of the flash
memory device’s operations. The CUI does not occupy an addressable memory location; it is the
mechanism through which the flash device is controlled.
Bus Operations Overview
Bus cycles to and from the device conform to standard microprocessor bus operations.
summarizes the bus operations and the voltage levels that must be applied to the device control
signals when operating within each device mode. Whenever CE# is asserted, the device is in an
active state; it is selected and its internal circuits are active. OE# and WE# determine whether
D[15:0] are outputs or inputs, respectively.
Read Mode
To perform a bus read operation, CE# and OE# must be asserted. CE# is the device-select control;
when active, it enables the flash memory device. OE# is the data-output control; when active, the
addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RST# must be
de-asserted. See
on page 39
on page 56
IL
or V
RST#
IH
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
for the control pins and V
IL
for details on reading from the flash array, and refer to
for details regarding all other available read states.
Enabled
Enabled
Enabled
Disabled
Enabled
Enabled
CE#
Section 7.1, “Read Operations” on page
X
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
PEN
≤ V
OE#
V
V
V
V
V
PENLK
X
X
IH
IH
IH
IL
IL
(1)
PENLK
, memory contents can be read but not altered.
WE#
V
V
V
V
V
or V
X
X
IH
IH
IH
IL
IL
(1)
PENH
ADV#
for V
X
X
X
X
X
X
X
PEN
. For outputs, X should be V
High-Z
High-Z
Driven
Driven
Driven
Driven
WAIT
Valid
24. Refer to
V
V
PENH
PEN
X
X
X
X
X
X
Section 14.0, “Special Modes”
Section 10.0, “Read Modes”
High-Z
High-Z
High-Z
D
D
Data
D
D
OUT
OUT
IN
IN
OL
or V
(default
mode)
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
OH
STS
V
.
IL
Table 14
Notes
3, 4
2
35