RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 41

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

10.3.1
10.3.2
Datasheet
Table 16. Read Configuration Register (Sheet 2 of 2)
Read Mode
The read mode (RM) bit selects synchronous burst mode or asynchronous page mode operation of
the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is
cleared, synchronous burst mode is selected.
Synchronous burst mode is used for array reads, whereas asynchronous page mode is used for
reading array data, Status Register information, Device ID information, and CFI information. Note
that when operating in synchronous burst mode, Status, ID, and CFI information will be driven
onto the bus on the next valid clock edge following the initial synchronous access delay, and will
remain on the bus for the duration of the access cycle.
Latency Count
The Latency Count bits, LC[3:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto D[15:0].
settings of LC[3:0]. See
frequencies.
14:11
5:3
2:0
10
9
8
7
6
Latency Count (LC[3:0])
Wait Polarity (WP)
Data Hold (DH)
Wait Delay (WD)
Burst Sequence (BS)
Clock Edge (CE)
Reserved (R)
Burst Length (BL[2:0])
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
Table 17 on page 42
0000 = Code 0. RFU
0001 = Code 1. RFU
0010 =Code 2
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 = Code 6
0111 = Code 7
1000 = Code 8
1001 = Code 9
1010 = Code 10
1011 - 1111 = Code 11 - Code 15. All these codes are RFU
0 = WAIT signal is active low
1 = WAIT signal is active high (default)
0 = Hold data for one clock
1 = Hold data for two clocks (default)
0 = WAIT de-asserted with valid data
1 = WAIT de-asserted one clock before valid data (default)
0 = Reserved
1 = Linear (default)
0 = falling edge
1 = rising edge (default)
000 - Cannot be changed
001 = RFU
010 = 8-word burst
011 = 16-word burst
111 = RFU (default)
Table 20 on page 42
for latency setting values matched for input clock
shows the data output latency for the valid
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