RC28F128K3C115 Intel, RC28F128K3C115 Datasheet - Page 45

• Manufacturer Part Number: RC28F128K3C115
• Description: IC FLASH 128MBIT 115NS 64BGA
• Manufacturer: Intel

Specifications of RC28F128K3C115

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: StrataFlash® FLASH
• Memory Size: 128M (8Mx16)
• Speed: 115ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-BGA
• Other names: 848521

11.0
11.1
11.2
Datasheet
Program Modes
The device supports three different programming methods: Word Programming, Write-Buffer
Programming, and Buffered Enhanced Factory Programming or Buffered-EFP. Successful
programming requires the addressed block to be unlocked. If the block is locked down, WP# must
be de-asserted and the block unlocked before attempting to program the array. An attempt to
program a locked block will result in the operation aborting, and SR[1] and SR[4] being set,
indicating a programming error. The following sections describe device programming in detail.
Word Programming
Word Programming is performed by executing the Word Program command. Word Programming
is a non-buffered operation and programs one word to the flash array based on the initial program
address A[A
register and analyze the bits. If the flash device is put in standby mode during a program operation,
the device will continue to program the word until the operation is complete; then the device will
enter standby mode. Refer to
flow on how to implement a word program operation.
During programming, the Write State Machine executes a sequence of internally-timed events that
program the desired data bits and verifies that the bits are sufficiently programmed. Programming
the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be
changed to ones only by erasing the block.
When programming has finished, Status Register bit SR4 set indicates a programming failure. If
SR3 is set, this indicates that the Write State Machine could not perform the Word Programming
operation because V
operation had attempted to program a locked block, causing the operation to abort.
After examining the status register, it should be cleared using the Clear Status Register command
before issuing a new command. Any valid command can follow, after Word Programming has
completed.
Write-Buffer Programming
The device features a 32-word Write Buffer to allow optimum programming performance. For
Write-Buffer Programming, data is first written to an on-chip write buffer, then programmed into
the flash memory array in buffer-size increments. Optimal performance is realized when
programming is buffer-size aligned to the 32-word write-buffer boundary. The write-buffer is
directly mapped to the flash array through A[A
decrease program performance. Buffered writes can improve system programming performance
more than 20X over non write-buffer programming.
To perform Write-Buffer Programming, the Write-to-Buffer Setup command, 0xE8, is issued along
with the block address (see
information is updated, and a read from the block address will return Status Register data showing
the write buffer’s availability. Note: Do not issue the Read Status Register command during this
sequence. SR7 indicates the availability of the write buffer for loading data. If SR7 is set, the write
MAX
:A
28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18
MIN
PEN
]. To determine the status of a word-program operation, poll the status
was outside of its acceptable limits. If SR1 is set, the Word Programming
Section 9.2, “Device Commands” on page
Figure 26, “Word Programming Flowchart” on page 71
MIN
+4:A
MIN
]. Unaligned buffered writes will
37). Status Register
for a detailed
45