HYB25D256160CF-5 Qimonda, HYB25D256160CF-5 Datasheet - Page 22

• Manufacturer Part Number: HYB25D256160CF-5
• Description: IC DDR SDRAM 256MBIT 60TFBGA
• Manufacturer: Qimonda

Specifications of HYB25D256160CF-5

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1007-2

1) 0 °C ≤
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions,
4) Peak to peak AC noise on
5)
6) Inputs are not recognized as valid until
7)
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
9) Values are shown per pin.
Rev. 2.4, 2007-07
03062006-8CCM-VPUW
Parameter
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
Supply Voltage, I/O Supply
Voltage
Input Reference Voltage
I/O Termination Voltage
(System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and
CK Inputs
Input Differential Voltage,
CK and CK Inputs
VI-Matching Pull-up Current
to Pull-down Current
Input Leakage Current
Output Leakage Current
Output High Current, Normal
Strength Driver
Output Low Current, Normal
Strength Driver
V
must track variations in the DC level of
V
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
TT
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
is not applied directly to the device.
T
A
≤ 70 °C;
V
DDQ
V
DDQ
= 2.5 V ± 0.2 V,
must be less than or equal to
V
REF
V
V
V
V
V
V
V
V
V
V
V
V
I
I
I
I
Symbol
I
OZ
OH
OL
may not exceed ± 2 %
DD
DD
DDQ
DDQ
SS
REF
TT
IH(DC)
IL(DC)
IN(DC)
ID(DC)
Ratio
,
V
SSQ
V
V
V
V
REF
REF
TT
DD
.
is a system supply for signal termination resistors, is expected to be set equal to
stabilizes.
= +2.5 V ± 0.2 V;
Min.
2.3
2.5
2.3
2.5
0
0.49 ×
V
V
–0.3
–0.3
0.36
0.71
–2
–5
—
16.2
REF
REF
– 0.04
+ 0.15
V
DDQ
V
V
REF.DC
DD
.
Electrical Characteristics and DC Operating Conditions
Typ.
2.5
2.6
2.5
2.6
0.5 ×
—
—
—
—
—
—
—
—
—
—
.
V
Values
22
REF
V
is also expected to track noise variations in
DDQ
Max.
2.7
2.7
2.7
2.7
0
0.51 ×
V
V
V
V
V
1.4
2
5
–16.2
—
REF
DDQ
REF
DDQ
DDQ
+ 0.04
– 0.15
+ 0.3
+ 0.3
+ 0.6
V
DDQ
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Unit Note/Test Condition
V
V
V
V
V
V
V
V
V
V
V
—
µA
µA
mA
mA
f
f
f
f
—
4)
5)
6)
6)
6)
6)7)
8)
Any input 0 V ≤
other pins not under test = 0 V
DQs are disabled; 0 V ≤
V
V
V
CK
CK
CK
CK
DDQ
OUT
OUT
≤ 166 MHz
> 166 MHz
≤ 166 MHz
> 166 MHz
9)
= 1.95 V
= 0.35 V
Internet Data Sheet
V
DDQ
3)
2)
TABLE 18
.
2)3)
V
IN
≤
1)
V
V
REF
DD
V
, and
; All
OUT
≤
9)