MAX6852AEE+T Maxim Integrated Products, MAX6852AEE+T Datasheet - Page 8

• Manufacturer Part Number: MAX6852AEE+T
• Description: IC VFD CTRLR MATRIX 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX6852AEE+T

• Display Type: Vacuum Fluorescent (VF)
• Configuration: 5 x 7 (Matrix)
• Interface: Serial
• Current - Supply: 3.5mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -

The PORT0 and PORT1 outputs can be individually
configured as either 625Hz, 1250Hz, or 2500Hz clocks
(OSC = 4MHz) intended for buzzer driving, the 4-wire
serial interface’s DOUT data output, blink or shutdown
status outputs, or general-purpose logic outputs.
The MAX6852 has two display modes (Table 1), select-
ed by the M bit in the configuration register (Table 21).
The display modes trade the maximum allowable num-
ber of digits (96/2 mode) against the availability of
annunciator segments (48/1 mode). Table 2 is the reg-
ister address map.
On initial power-up, all control registers are reset, the
display segment and annunciator data are cleared,
intensity is set to minimum, and shutdown is enabled
(Table 3).
The MAX6852 uses 48 character registers (48/1 mode)
(Table 4) or 96 character registers (96/2 mode) (Table
5) to store the 5 x 7 characters (Table 6). Each digit is
represented by 1 byte of memory. The data in the char-
acter registers does not control the character segments
directly. Instead, the register data is used to address a
character generator, which stores the data of the 128-
character font (Table 7). The lower 7 bits of the charac-
ter data (D6 to D0) select a character from the font
table. The most significant bit (MSB) of the register data
(D7) controls the DP segment of the digit; it is set to
light the DP, cleared to leave it unlit.
The character registers address maps are shown in
Table 4 (48/1 mode) and Table 5 (96/2 mode).
In 48/1 mode, the character registers use a single
address range 0x20 to {0x20 + g}, where g is the value
in the grids register (Table 24). The 48/1 mode upper
address limit, when g is 0x2F, is therefore 0x4F. The
address range 0x50 to 0x7F is used for annunciator
data in 48/1 mode.
In 96/2 mode, the character registers use two address
ranges. The first row’s address range is 0x20 to
{0x20 + g}. The second row’s address range is 0x50 to
{0x50 + g}. Therefore, in 96/2 mode, the character regis-
ters are only one contiguous memory range when a 48-
grid display is used.
The font is a 5 x 7 matrix comprising 104 characters in
ROM, and 24 user-definable characters. The selection
from the total of 128 characters is represented by the
4-Wire Interfaced, 5
Fluorescent Display Controller
8
_______________________________________________________________________________________
Character Generator Font Mapping
Character Registers
Initial Power-Up
Display Modes
✕
7 Matrix Vacuum-
lower 7 bits of the 8-bit digit registers. The MSB, shown
as x in the ROM map (Table 7), controls the DP seg-
ment of the digit; it is set to light the DP, cleared to
leave it unlit.
The character map follows the Arial font for 96 charac-
ters in the x0100000 through x1111111 range. The first
32 characters map the 24 user-definable positions
(RAM00 to RAM23), plus eight extra common charac-
ters in ROM.
The 24 user-definable characters are represented by
120 entries of 7-bit data, five entries per character, and
are stored in the MAX6852’s internal RAM.
The 120 user-definable font data entries are written and
read through a single register, address 0x05. An
autoincrementing font address pointer in the MAX6852
indirectly accesses the font data. The font address
pointer can be written, setting one of 120 addresses
between 0x00 and 0xF7, but cannot be read back. The
font data is written to and read from the MAX6852 indi-
rectly, using this font address pointer. Unused font
locations can be used as general-purpose scratch
RAM, noting that the font registers are only 7 bits wide,
not 8.
Figure 5. Block Diagram of VFD Tube Driver and VFD Tube
VFBLANK
VFLOAD
VFCLK
VFDIN
O0
O0
O1
O1
SERIAL-TO-PARALLEL SHIFT REGISTER
VFD TUBE DRIVER
O2
O2
VFD TUBE SIMPLIFIED
User-Defined Fonts
LATCHES
ON
ON