ADE7763ARSZRL Analog Devices Inc, ADE7763ARSZRL Datasheet - Page 52

IC ENERGY METERING 1PHASE 20SSOP

ADE7763ARSZRL

Manufacturer Part Number
ADE7763ARSZRL
Description
IC ENERGY METERING 1PHASE 20SSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADE7763ARSZRL

Input Impedance
390 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
3mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP (0.200", 5.30mm Width)
Meter Type
Single Phase
Ic Function
Single-Phase Active And Apparent Energy Metering IC
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
Lead Free Status / Rohs Status
Compliant
Other names
ADE7763ARSZRL
ADE7763ARSZRLTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7763ARSZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADE7763
INTERRUPT STATUS REGISTER (0x0B),
RESET INTERRUPT STATUS REGISTER (0x0C),
INTERRUPT ENABLE REGISTER (0x0A)
The status register is used by the MCU to determine the source of an interrupt request ( IRQ ). When an interrupt event occurs, the
corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register,
the IRQ logic output will go active low. When the MCU services the interrupt, it must first carry out a read from the interrupt status
register to determine the source of the interrupt.
Table 12.
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
(POWER POSITIVE TO NEGATIVE)
(POWER NEGATIVE TO POSITIVE)
Interrupt
Flag
AEHF
SAG
CYCEND
WSMP
ZX
TEMP
RESET
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
PPOS
PNEG
RESERVED
(ZERO-CROSSING TIMEOUT)
(VAENERGY IS HALF FULL)
(VAENERGY OVERFLOW)
Description
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
Indicates that an interrupt was caused by a sag on the line voltage.
Indicates the end of energy accumulation over an integral number of half line cycles, as defined by the content
of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit is set to Logic 0 on the rising and falling edge of the voltage waveform, see the Zero-Crossing
Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset for software and hardware resets. The corresponding enable bit has no function in
the interrupt enable register, i.e., this status bit is set at the end of a reset, but cannot be enabled to cause an
interrupt.
Indicates that the active energy register has overflowed.
Indicates that the waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that the waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt occurred because the apparent energy register, VAENERGY, is more than half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for a specified number of
line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
RESERVED
VAEOF
VAEHF
PNEG
PPOS
ZXTO
PKV
PKI
15 14 13 12 11 10
0
0
Figure 87. Interrupt Status/Interrupt Enable Register
0
0
0
0
Rev. B | Page 52 of 56
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
AEHF
(ACTIVE ENERGY HALF FULL)
SAG
(SAG ONLINE VOLTAGE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZX
(ZERO CROSSING)
TEMP
(TEMPERATURE DATA READY)
RESET
(END OF SOFTWARE/HARDWARE RESET)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)

Related parts for ADE7763ARSZRL