ADE7763ARSZRL Analog Devices Inc, ADE7763ARSZRL Datasheet - Page 53

IC ENERGY METERING 1PHASE 20SSOP

ADE7763ARSZRL

Manufacturer Part Number
ADE7763ARSZRL
Description
IC ENERGY METERING 1PHASE 20SSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADE7763ARSZRL

Input Impedance
390 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
3mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SSOP (0.200", 5.30mm Width)
Meter Type
Single Phase
Ic Function
Single-Phase Active And Apparent Energy Metering IC
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
SSOP
No. Of Pins
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADE7763ZEB - BOARD EVALUATION FOR ADE7763
Lead Free Status / Rohs Status
Compliant
Other names
ADE7763ARSZRL
ADE7763ARSZRLTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7763ARSZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
CH1OS REGISTER (0x0D)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch the digital integrator on and off in
Channel 1, and Bits 0 to 5 indicate the amount of offset correction in Channel 1. Table 13 summarizes the function of this register.
Table 13. CH1OS Register
Bit
Location
0 to 5
6
7
Bit
Mnemonic
OFFSET
Not Used
INTEGRATOR
DIGITAL INTEGRATOR SELECTION
Description
The 6 LSBs of the CH1OS register control the amount of dc offset correction in the Channel 1 ADC. The 6-bit
offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset correction.
Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset correction is positive, and a 1
indicates the offset correction is negative.
This bit is not used.
This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by setting
this bit. This bit is set to 0 by default.
0 = DISABLE
1 = ENABLE
NOT USED
Figure 88. Channel 1 Offset Register
0
7
Rev. B | Page 53 of 56
0
6
0
5
4
0
0
3
2
0
1
0
0
0
SIGN AND MAGNITUDE CODED
OFFSET CORRECTION BITS
ADDR: 0x0D
ADE7763

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