ISL6173DRZA Intersil, ISL6173DRZA Datasheet - Page 11

• Manufacturer Part Number: ISL6173DRZA
• Description: IC CTRLR HOT SWAP DUAL LV 28QFN
• Manufacturer: Intersil
• Type: Hot-Swap Controllerr

Specifications of ISL6173DRZA

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 2.25 V ~ 3.63 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN Exposed Pad
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 15. If one channel goes down for any reason, the
other one will too. One important thing to note here is that
only the overcurrent latch-off mode will work. Auto-retry
feature WILL NOT work. Retry must be controlled manually
through EN.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
3. ENx pin, when pulled low (below it’s specified threshold),
4. SSx cap begins to charge up through the internal 10µA
charge pump immediately powers up.
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
enables the respective channel.
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
11
ISL6173
State Diagram
This is shown in Figure 16. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
5. SS cap begins to charge but the corresponding CTx cap
6. Fault (FLT) remains deasserted (stays high) and the
7. If the load current on the output exceeds the set current
8. If the voltage on UV pin exceeds 633mV threshold as a
9. At the end of the SS interval, the SS cap voltage reaches
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
is held discharged.
output voltage continues to rise.
limit for greater than the OC timeout period, FLT gets
asserted and the channel shutdown occurs.
result of rising Vo, the Power Good (PG) output goes
active.
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
January 3, 2006
FN9186.3