MAX5952AEAX+ Maxim Integrated Products, MAX5952AEAX+ Datasheet - Page 7

• Manufacturer Part Number: MAX5952AEAX+
• Description: IC PSE CNTRLR FOR POE 36-SSOP
• Manufacturer: Maxim Integrated Products
• Type: Power Over Ethernet Controller (PoE)r

Specifications of MAX5952AEAX+

• Applications: Remote Peripherals (Industrial Controls, Cameras, Data Access)
• Internal Switch(s): No
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-BSOP (0.300", 7.5mm Width)
• Product: Controllers & Switches
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.71 V
• Power Dissipation: 941 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Supply Current: 4.8 mA
• Input Voltage: 60V
• Digital Ic Case Style: SSOP
• No. Of Pins: 36
• Uvlo: 28.5V
• Frequency: 400kHz
• Interface: I2C
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Controller Type: Power Over Ethernet PD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
V
wise.) (Note 2)
Note 2: Limits to T
Note 3: Default values. The current-limit thresholds are programmed through the I
Note 4: Functional test is performed over thermal shutdown entering test mode.
Note 5: Default values. The startup and fault times can be also programmed through the I
Note 6: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 7: AC disconnect works only if (V
Note 8:
Note 9: R
Note 10: Guaranteed by design. Not subject to production testing.
Differential Nonlinearity
ADC Absolute Accuracy
TIMING CHARACTERISTICS (For 2-Wire Fast Mode, Note 10)
Serial-Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time for a START
Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition (Sr)
Data Hold Time
Data in Setup Time
Rise Time of Both SDA and
SCL Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line
Pulse Width of Spike
Suppressed
AGND
AGND
= +48V, V
= 32V to 60V, V
PARAMETER
Map and Description section).
and Description section).
t
rent at DET_ during phase 1 and 2 of the detection.
DISC
D
= (V
can also be programmed through the serial interface (R16H) (see the Register Map and Description section).
DGND
OUT_2
A
_______________________________________________________________________________________
= -40°C are guaranteed by design.
EE
= +48V, V
- V
= 0V, V
OUT_1
DD
) / (I
DD
SYMBOL
t
t
t
t
t
to V
HD, STA
HD, DAT
SU, DAT
SU, STO
SU, STA
DET_2
t
t
= (V
DNL
t
f
HIGH
LOW
SCL
BUF
C
t
t
t
SP
R
F
High-Power, Quad, PSE Controller
DGND
B
DD
DGND
- I
- V
DET_1
= +3.3V, all voltages are referenced to V
DGND
V
V
V
+ 3.3V), T
SENSE
SENSE
SENSE
). V
) ≥ 3V and DGND is connected to AGND.
OUT_1
= 100mV
= 250mV
= 400mV
A
= +25°C. Currents are positive when entering the pin and negative other-
, V
OUT_2
CONDITIONS
for Power-Over-Ethernet
, I
DET_2
and I
DET_1
2
C-compatible serial interface (see the Register
EE
, unless otherwise noted. Typical values are at
represent the voltage at OUT_ and the cur-
2
C serial interface (see the Register Map
0.1C
0.1C
(240)
(390)
20 +
20 +
MIN
(91)
186
100
1.2
0.6
1.2
0.6
0.6
0.6
5B
F0
0
B
B
(252)
(406)
TYP
(98)
196
0.1
FC
62
(104)
(264)
(422)
MAX
1A6
108
400
150
300
300
400
68
50
UNITS
(Dec)
LSB
Hex
kHz
pF
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
7