LTC4214-1CMS#PBF Linear Technology, LTC4214-1CMS#PBF Datasheet - Page 9

• Manufacturer Part Number: LTC4214-1CMS#PBF
• Description: IC CTRLR HOTSWAP NEGVOLT 10MSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4214-1CMS#PBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 6 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• Linear Misc Type: Negative Low Voltage
• Family Name: LTC4214-1
• Package Type: MSOP
• Operating Supply Voltage (min): -6V
• Operating Supply Voltage (max): -16V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3mm
• Product Height (mm): 0.86mm
• Product Length (mm): 3mm
• Mounting: Surface Mount
• Pin Count: 10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI FU CTIO S
UV (Pin 9): Undervoltage Input. The active high threshold
at the UV pin is set at 2.25V with respect to V
0.25V hysteresis. If UV < 2V, PWRGD pulls high, both
GATE and TIMER pull low. If UV rises above 2.25V, this
initiates an initial timing cycle followed by GATE start-up.
The internal UVLO at V
resets an internal fault latch. A 1nF to 10nF capacitor at UV
prevents transients and switching noise from affecting the
UV thresholds and prevents glitches at the GATE pin.
TIMER (Pin 10): Timer Input. TIMER is used to generate
an initial timing delay at start-up and to delay shutdown in
the event of an output overload (circuit breaker fault).
TIMER starts an initial timing cycle when the following
conditions are met: UV is high, OV is low, V
TIMER pin is low, GATE is lower than V
and V
charges C
V
pulls low and GATE is activated.
TMRH
U
SENSE
(3V), the timing cycle terminates, TIMER quickly
T
U
, generating a time delay. If C
– V
EE
< V
U
IN
CB
always overrides UV. A low at UV
. A pull-up current of 5 A then
GATEL
IN
EE
T
clears UVLO,
and exhibits
, SS < 0.2V,
charges to
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 40 A pull-up current charging
C
timer pull-up has an additional current of 8 • I
drops below 50mV before TIMER reaches 3V, a 5 A pull-
down current slowly discharges the C
eventually integrates up to the V
breaker trips, GATE quickly pulls low and PWRGD pulls
high. The LTC4214-1 TIMER pin latches high with a 5 A
pull-up source. This latched fault is cleared by either
pulling TIMER low with an external device or by pulling UV
below 2V. The LTC4214-2 starts a shutdown cooling cycle
following an overcurrent fault. This cycle consists of 4
discharging ramps and 3 charging ramps. The charging
and discharging currents are 5 A and TIMER ramps
between its 1.7V and 3V thresholds. At the completion of
a shutdown cooling cycle, the LTC4214-2 attempts a start-
up cycle.
T
. If DRAIN is approximately 4.2V during this cycle, the
LTC4214-1/LTC4214-2
TMRH
T
threshold, the circuit
. In the event that C
DRN
. If SENSE
421412f
9
T