LTC4240CGN Linear Technology, LTC4240CGN Datasheet - Page 15

• Manufacturer Part Number: LTC4240CGN
• Description: IC CTRLR HOTSWAP CPCI I2C 28SSOP
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4240CGN

• Applications: CompactPCI™
• Internal Switch(s): No
• Voltage - Supply: 3.3V, 5V, ±12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Table 3 shows the definition for each data bit. PWRGD,
FAULT, RESETIN, and RESETOUT external pins can be
monitored. PRSNT1# and PRSNT2# are PCI signals that
provide information on the power requirements of the
board. Refer to PCI local bus specifications for a detailed
description. FAULTCODE1 and FAULTCODE0 are two in-
ternal binary encoded signals that, along with FAULT,
indicate which of the four supplies generated a fault. Note
that the FAULTCODE signals are valid only when FAULT
has been asserted low. See Table 4 for description.
Status LED
The main function of the LED is to alert the user when it is
permissible to physically extract the board. The LED
output of the LTC4240 is an open drain N-channel device
capable of sinking 10mA from an externally connected
LED. This LED lights up when RESETOUT
(LOCAL_PCI_RST#) is asserted. Upon application of Early
Power, the long 5V pins will power up the LTC4240 and
light up the Status LED. It will remain on until PWRGD
(HEALTHY#) is asserted and RESETIN (PCI_RST#) is de-
asserted, and the board enters normal operation. Note that
this LED can also be turned on via the I
CPCI Connection Pin Sequence
The staggered length of the CPCI male connector pins
ensures that all power supplies are physically connected
Table 3. STATUS Byte Definitions
S7
S6
S5
S4
S3
S2
S1
S0
SDA
SCL
START
1
0
Logic state of the PRSNT2# pin
Logic state of the PRSNT1# pin
Logic state of the PWRGD pin
Logic state of the RESETOUT pin
Logic state of the RESETIN pin
FAULTCODE1 (see Table 4)
FAULTCODE0 (see Table 4)
Logic state of the FAULT pin
2
1
U
ADDR 4
3
U
ADDRESS BYTE
ADDR 3
4
ADDR 2
W
5
2
C 2-wire interface.
ADDR 1
6
ADDR 0
Figure 3. Receive Byte Protocol
7
U
R/WR=1
8
ACK
9
to the LTC4240 before back-end power is allowed to ramp
(BD_SEL# asserted low). The long pins, which include 5V,
3.3V, V(I/O) and GND mate first. The short pins, which
includes BD_SEL# (OFF/ON), mate last. At least one long
5V power pin must be connected to the LTC4240 in order
for the PRECHARGE voltage to be available during Early
Power. The external components connected to the
precharge pin require long 3.3V.
The following is a typical hot plug sequence:
1. ESD clips make contact.
2. Long power and ground pins make contact and Early
3. Medium length pins make contact. There are six 5V and
Table 4. FAULTCODE Encoding Description for Receive Byte
FAULTCODE0
S7
1
Power is established (see Early Power section). The 1V
PRECHARGE voltage becomes valid at this stage. Power
is applied to the pull-up resistors connected to FAULT,
PWRGD and OFF/ON pins. The status LED is lit, indicat-
ing that the plug-in board is in the process of being
connected (LOCAL_PCI_RST# is asserted). All power
switches are off.
eight 3.3V medium length power pins, bringing the 5V
total to 8 pins and the 3.3V total to 10 pins. The
maximum DC current for the 3.3V and 5V supplies is
10A and 8A, respectively. The I
initialized to allow seamless CPCI Hot Swap operation.
The LTC4240 can be used as a Hot Swap controller
without ever establishing I
FAULT and PWRGD continue to be pulled up high at this
LO
LO
HI
HI
X
S6
2
S5
3
FAULTCODE1
DATA BYTE
S4
4
LO
LO
HI
HI
X
S3
5
S2
6
FAULT
LO
LO
LO
LO
2
HI
C communication. Both
S1
7
2
C command latch is
S0
Supply Causing Fault
8
LTC4240
ACK
9
12V
V
None
3V
5V
EEIN
IN
IN
IN
15
STOP
4240 F03
4240f