DS1873T+ Maxim Integrated Products, DS1873T+ Datasheet - Page 13

• Manufacturer Part Number: DS1873T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1873T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1873T+000

Table 1. Acronyms
Figure 1. Power-Up Timing
ACRONYM
SFF-8472
ROSA
TOSA
SFP+
AGC
ADC
DAC
APC
APD
ATB
LOS
LUT
SEE
SFP
TXP
BM
TIA
SFF
NV
QT
TE
BIAS SAMPLE
SFP+ Controller with Analog LDD Interface
Analog-to-Digital Converter
Automatic Gain Control
Automatic Power Control
Avalanche Photodiode
Alarm Trap Bytes
Burst Mode
Digital-to-Analog Converter
Loss of Signal
Lookup Table
Nonvolatile
Quick Trip
Tracking Error
Transimpedance Amplifier
Receiver Optical Subassembly
Shadowed EEPROM
Small Form Factor
Document Defining Register Map of SFPs
and SFFs
Small Form Factor Pluggable
Enhanced SFP
Transmit Optical Subassembly
Transmit Power
MOD DAC
BIAS DAC
V
______________________________________________________________________________________
CC
V
DEFINITION
POA
t
ISTEP
INIT
2x ISTEP
3x ISTEP
1
4x ISTEP
2
3
4
On power-up, the DS1873 sets the MOD and BIAS
DACs to 0. After a temperature conversion is complet-
ed and if the VCC LO alarm is enabled, an additional
V
alarm level is required before the MOD DAC is updated
with the value determined by the temperature conver-
sion and the modulation LUT.
When the MOD DAC is set, the BIAS DAC is set to a
value equal to ISTEP (see Figure 1). The startup algo-
rithm checks if this bias current causes a feedback
voltage above the APC set point, and if not, it continues
increasing the BIAS DAC by ISTEP until the APC set-
point is exceeded. When the APC set point is exceed-
ed, the device begins a binary search to quickly reach
the bias current corresponding to the proper power
level. After the binary search is completed, the APC
integrator is enabled and single LSB steps are used to
tightly control the average power.
The TXP HI, TXP LO, HBAL, and BIAS MAX QT alarms
are masked until the binary search is completed.
However, the BIAS MAX alarm is monitored during this
time to prevent the BIAS DAC from exceeding IBIASMAX.
During the bias current initialization, the BIAS DAC is
not allowed to exceed IBIASMAX. If this occurs during
the ISTEP sequence, then the binary search routine is
5
t
CC
SEARCH
conversion above the customer-defined VCC LO
6
BINARY SEARCH
7
8
BIAS and MOD Output Control
9
10
APC INTEGRATOR ON
11
During Power-Up
12
13
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