DS1873T+ Maxim Integrated Products, DS1873T+ Datasheet - Page 25

• Manufacturer Part Number: DS1873T+
• Description: IC CTLR SFP+ ANLG LDD 28-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Laser Diode Controllerr

Specifications of DS1873T+

• Number Of Channels: 1
• Voltage - Supply: 2.85 V ~ 3.9 V
• Current - Supply: 2.5mA
• Operating Temperature: -40°C ~ 95°C
• Package / Case: 28-WFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1873T+000

Figure 17. Example I
A)
B)
C)
D)
TYPICAL I
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
EXAMPLE I
START
= 1, the master reads data from the slave. If an
incorrect slave address is written, the DS1873
assumes the master is communicating with another
I
next START condition is sent. If the main device’s
slave address is programmed to be A0h, access to
the auxiliary memory is disabled.
Memory address: During an I
the DS1873, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
Writing a single byte to a slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s
acknowledgement during all byte-write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0),
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h
TO C8h AND C9h
TWO-BYTE READ
-READ C8h AND C9h
2
C device and ignores the communications until the
2
C WRITE TRANSACTION
2
MSB
C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
1
0
SFP+ Controller with Analog LDD Interface
1
ADDRESS*
SLAVE
2
______________________________________________________________________________________
0
C Timing
START
START
START
START
0
0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1
A2h
A2h
A2h
A2h
WRITE
READ/
LSB
R/W
2
C write operation to
SLAVE
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
ACK
I
2
MSB
1 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0
1 1 0 0 1 0 0 0
1 1 0 0 1 0 0 0
b7
C Protocol
BAh
BAh
C8h
C8h
b6
b5
REGISTER ADDRESS
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
b4
b3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
REPEATED
REPEATED
START
START
b2
00h
01h
b1
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The
DS1873 writes 1 to 8 bytes (one page or row) with a
single write transaction. This is internally controlled
by an address counter that allows data to be written
to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages results in the address
counter wrapping around to the beginning of the
present row.
For example, a 3-byte write starts at address 06h
and writes three data bytes (11h, 22h, and 33h) to
three “consecutive” addresses. The result is that
addresses 06h and 07h would contain 11h and 22h,
respectively, and the third data byte, 33h, would be
written to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
LSB
SLAVE
SLAVE
b0
ACK
ACK
A3h
A3h
SLAVE
ACK
0 1 1 1 0 1 0 1
STOP
75h
SLAVE
SLAVE
ACK
ACK
MSB
b7
b6
DATA IN BAh
DATA IN C8h
SLAVE
ACK
DATA
DATA
b5
STOP
b4
DATA
MASTER
MASTER
b3
NACK
ACK
b2
STOP
DATA IN C9h
b1
DATA
LSB
b0
SLAVE
ACK
MASTER
NACK
STOP
STOP
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