PCA9624PW,118 NXP Semiconductors, PCA9624PW,118 Datasheet - Page 16

• Manufacturer Part Number: PCA9624PW,118
• Description: IC LED DRIVER RGBA 24-TSSOP
• Manufacturer: NXP Semiconductors
• Type: RGBA LED Driverr

Specifications of PCA9624PW,118

• Package / Case: 24-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: RGBA
• Frequency: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Voltage - Output: 40V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 100mA
• Internal Switch(s): Yes
• Low Level Output Current: 20 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 10 mA
• Maximum Power Dissipation: 100 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 03118 863 9352

NXP Semiconductors
8. Characteristics of the I
PCA9624_2
Product data sheet
8.1.1 START and STOP conditions
8.1 Bit transfer
8.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 8.
Fig 9.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
Rev. 02 — 26 August 2009
S
9).
Figure
data valid
data line
stable;
10).
Figure
8-bit Fm+ I
allowed
change
of data
8).
2
C-bus 100 mA 40 V LED driver
STOP condition
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PCA9624
P
© NXP B.V. 2009. All rights reserved.
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