ICB1FL02G Infineon Technologies, ICB1FL02G Datasheet - Page 11

• Manufacturer Part Number: ICB1FL02G
• Description: IC SMART BALLAST CONTROL PDSO-18
• Manufacturer: Infineon Technologies
• Type: PFC/Ballast Controllerr

Specifications of ICB1FL02G

• Frequency: 20 ~ 100 kHz
• Current - Supply: 650µA
• Voltage - Supply: 10.5 V ~ 17.5 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: DSO-18
• Packages: PG-DSO-18
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / Rohs Status: Details
• Other names: ICB1FL02GXT; SP000204703

3.2
PFC is starting with a fixed frequent operation (ca. 25kHz), beginning with an on-time of 1µs and an off-time of
40µs. The on-time is enlarged every 400µs to a maximum on-time of 23µs. The control switches over into critical
conduction mode (CritCM) operation as soon as a sufficient ZCD signal is available. There is an overvoltage
threshold at 109% of rated Bus voltage that stops PFC Gate drive as long as the Bus voltage has reached a level
of 105% of rated Bus voltage again. The compensation of the voltage control loop is completely integrated. The
internal reference level of the Bus voltage sense (PFCVS) is 2,5V with high accuracy.
The PFC control operates in CritCM in the range of 23µs > on-time > 2,3µs. For lower loads the control operates
in discontinuous conduction mode (DCM) with an on-time down to 0,5µs and an increasing off-time. With this
control method the PFC preconverter covers a stable operation from 100% of load to 0,1% .
Figure 5
Overvoltage, undervoltage and open loop detection at pin PFCVS are sensed by analog comparators. The BUS
voltage loop control is provided by a 8bit sigma-delta A/D-Converter with a sampling rate of 400µs and a resolution
of 4mV/bit. So a range of +/- 0,5V from the reference level of 2,50V is covered. The digital error signal has to pass
a digital notch filter in order to suppress the AC voltage ripple of twice of the mains frequency. A subsequent error
amplifier with PI characteristic cares for stable operation of the PFC preconverter.
The zero current detection is sensed by a separate pin PFCZCD. The information of finished current flow during
demagnetization is required in CritCM and in DCM as well. The input is equipped with a special filtering including
a blanking of typically 500ns and is combined with a large hysteresis between the thresholds of typically 0,5V and
1,5V. In case of bad coupling between primary inductor winding and secondary ZCD-winding an additional filtering
by a capacitor at ZCD pin might be necessary in order to avoid mistriggering by long lasting oscillations during
switching slopes of the PFC MOSFET.
Figure 6
Datasheet Version 2.1
PFC Preconverter
Circuit Diagram of the PFC preconverter section.
Structure of the mixed digital and analog control of PFC preconverter.
PFCVS
SRate 400µs
Res 4mV/bit
Σ∆-ADC
90 ...
270 VAC
L
RFI
D1...4
109% +/-2,0%
Undervoltage
73% +/- 2,5%
15% +/- 20%
Overvoltage
Open Loop
Detection
Notch
Filter
C1
R1
R2
Vcc
L1
PI Loop
Control
D9
Q1
11
C2
R6
D5
C7
C3 R9
R3
R7
R8
R4
1,50V / 0,5V
Overcurrent
Pulse width
1,0V +/-5%
Generator
Protection
600kHz
Start-up
Clock
ZCD
VBUS
PFCZCD
PFCGD
PFCVS
PFCCS
R5 R12 R13
Functional Description
Reference
HSGD
HSVCC
HSGND
LSGD
LSCS
+/-1,5%
Driver
2,50V
Gate
PFCZCD
PFCCS
PFCGD
September 2008
ICB1FL02G