FAN7383MX_WS Fairchild Semiconductor, FAN7383MX_WS Datasheet - Page 14

• Manufacturer Part Number: FAN7383MX_WS
• Description: IC GATE DVR HALF BRIDGE 14-SOIC
• Manufacturer: Fairchild Semiconductor
• Type: High Side Driverr

Specifications of FAN7383MX_WS

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 500ns
• Current - Peak: 350mA
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 15 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Product: Half-Bridge Drivers
• Rise Time: 100 ns
• Fall Time: 80 ns
• Supply Voltage (max): 20 V
• Supply Voltage (min): 15 V
• Supply Current: 650 uA
• Maximum Power Dissipation: 1 W
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Maximum Turn-off Delay Time: 170 ns
• Maximum Turn-on Delay Time: 670 ns
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Output Current: 350 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FAN7383 Rev. 1.0.3
© 2006 Fairchild Semiconductor Corporation
Typical Application Information
1. Normal Operating Consideration
The FAN7383 is a single PWM input half-bridge gate-
drive IC with programmable dead-time and shutdown
function.
The dead-time is set with a resistor (R
The wide dead-time programming range provides the
flexibility to optimize drive signal timing for a selection of
switching devices (MOSFET or IGBT) and applications.
The
accommodates resistor values from 0Ω to 200kΩ with a
dead-time proportional to the R
Grounding the DT pin programs the FAN7383 to drive
both outputs with minimum dead time.
If the SD pin voltage decrease below 1.2V in normal
operation, the IC enters the shutdown mode.
2. Under-Voltage Lockout (UVLO)
The FAN7383 has an under-voltage lockout (UVLO)
protection circuitry for high and low side channels to
prevent malfunction when V
specified threshold voltage. The UVLO circuitry monitors
the supply voltage (V
(V
BS
) independently.
turn-on
time
DD
) and bootstrap capacitor voltage
delay
DD
DT
or V
circuitry
resistance.
BS
DT
is lower than the
) at the DT pin.
(Dead-Time)
14
3. Layout Consideration
For optimum performance of high- and low-side gate
drivers, cannot be achieved without taking due
considerations must be taken during printed circuit board
(PCB) layout.
3.1 Supply Capacitors
If the output stages are able to quickly turn on the
switching device with high value of current, the supply
capacitors must be placed as close as possible to the
device pins (V
and V
inductance and resistance.
3.2 Gate Drive Loop
Current loops behave like an antenna, able to receive
and transmit noise. To reduce the noise coupling/
emission and improve the power switch turn-on and off
performances, gate drive loops must be reduced as
much as possible.
3.3 Ground Plane
Ground plane must not be placed under or nearby the
high-voltage floating side to minimize noise coupling.
S
for the floating supply) to minimize parasitic
DD
and GND for the ground-tied supply, V
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B