FAN7383MX_WS Fairchild Semiconductor, FAN7383MX_WS Datasheet - Page 5

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FAN7383MX_WS

Manufacturer Part Number
FAN7383MX_WS
Description
IC GATE DVR HALF BRIDGE 14-SOIC
Manufacturer
Fairchild Semiconductor
Type
High Side Driverr
Datasheet

Specifications of FAN7383MX_WS

Configuration
Half Bridge
Input Type
Non-Inverting
Delay Time
500ns
Current - Peak
350mA
Number Of Configurations
1
Number Of Outputs
2
High Side Voltage - Max (bootstrap)
600V
Voltage - Supply
15 V ~ 20 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Product
Half-Bridge Drivers
Rise Time
100 ns
Fall Time
80 ns
Supply Voltage (max)
20 V
Supply Voltage (min)
15 V
Supply Current
650 uA
Maximum Power Dissipation
1 W
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Bridge Type
Half Bridge
Maximum Turn-off Delay Time
170 ns
Maximum Turn-on Delay Time
670 ns
Minimum Operating Temperature
- 40 C
Number Of Drivers
2
Output Current
350 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FAN7383 Rev. 1.0.3
© 2006 Fairchild Semiconductor Corporation
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. T
Notes:
2. When mounted on 76.2 x 114.3 x 1.6mm PCB. (FR-4 glass epoxy material).
3. Please refer to:
4. Do not exceed P
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages
P
Symbol
Symbol
dV
D
GND
T
V
V
V
V
V
V
V
V
(2)(3)(4)
V
V
θ
V
V
V
V
T
T
STG
HO
HO
DD
LO
DD
SD
S
JA
LO
DT
IN
IN
A
B
S
S
B
J
/dt
High-side offset voltage
High-side floating supply voltage
High-side floating output voltage HO1, HO2
Low-side and logic fixed supply voltage
Low-side output voltage LO1, LO2
Logic input voltage (IN)
Shutdown logic input voltage
Dead-time control voltage
Logic ground
Allowable offset voltage slew rate
Power dissipation
Thermal resistance, junction-to-ambient
Junction temperature
Storage temperature
High-side floating supply voltage
High-side floating supply offset voltage
Low-side supply voltage
High-side (HO) output voltage
Low-side (LO) output voltage
Logic input voltage (IN)
Ambient temperature
D
under any circumstances.
Parameter
Parameter
A
= 25°C unless otherwise specified.
5
Condition
V
V
V
Min.
DD
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
S
B
-0.3
-25
-25
V
6-V
Min.
GND
GND
S
-40
V
15
V
V
V
V
+15
V
V
S
DD
Max.
DD
DD
DD
DD
B
B
625
150
110
150
5.0
1.0
25
50
+0.3
+0.3
+0.3
+0.3
+0.3
+0.3
V
Max.
600
125
S
V
V
20
V
+20
DD
DD
B
www.fairchildsemi.com
Unit
V/ns
°C/W
°C
°C
W
V
V
V
V
V
V
V
V
V
Unit
°C
V
V
V
V
V
V

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