IRS21844SPBF International Rectifier, IRS21844SPBF Datasheet - Page 9

• Manufacturer Part Number: IRS21844SPBF
• Description: IC DRIVER HALF-BRIDGE 14-SOIC
• Manufacturer: International Rectifier

Specifications of IRS21844SPBF

• Configuration: Half Bridge
• Input Type: Non-Inverting
• Delay Time: 680ns
• Current - Peak: 1.9A
• Number Of Configurations: 1
• Number Of Outputs: 2
• High Side Voltage - Max (bootstrap): 600V
• Voltage - Supply: 10 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The circuit shown in Figure 11 depicts a half bridge circuit with parasitic elements shown; Figures 12 and 13
show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic
inductances in the power circuit from the die bonding to the PCB tracks are lumped together in L
for each switch. When the high-side switch is on, V
associated with the power switch and the parasitic elements of the circuit. When the high-side power
switch turns off, the load current can momentarily flow in the low-side freewheeling diode due to the
inductive load connected to V
from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage
between V
pin).
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative V
transient voltage can exceed this range during some events such as short circuit and over-current
shutdown, when di/dt is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s
demanding applications. An indication of the IRS2184(4)’s robustness can be seen in Figure 14, where there
is represented the IRS2184(4) Safe Operating Area at V
negative V
viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs
transients fall inside SOA.
Figure 9: Parasitic Elements
Q1
Q2
DC+ BUS
V
DC- BUS
S1
S
S1
transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage;
and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V
L
L
L
L
C1
E1
C2
E2
D1
D2
S1,
for instance (the load is not shown in these figures). This current flows
Figure 10: V
OFF
ON
Q1
Q2
DC+ BUS
V
DC- BUS
S 1
+
V
+
-
V
-
IRS2184/IRS21844(S)PbF
s
S1
LC1
LE1
D2
positive
BS
is below the DC+ voltage by the voltage drops
=15V based on repetitive negative V
I
U
Figure 11: V
OFF
OFF
Q1
Q2
DC+ BUS
V
DC- BUS
S1
s
+
V
+
negative
-
V
-
LE 2
LC 2
D1
+
-
V
D2
S
spikes. A
C
I
U
and L
E
S
S
9