ISL6610ACRZ-T Intersil, ISL6610ACRZ-T Datasheet - Page 6

• Manufacturer Part Number: ISL6610ACRZ-T
• Description: IC MOSFET DRVR DUAL SYNC 16-QFN
• Manufacturer: Intersil

Specifications of ISL6610ACRZ-T

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Delay Time: 18ns
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 36V
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Peak: -

Timing Diagram
Operation and Adaptive Shoot-Through Protection
Designed for high speed switching, the ISL6610, ISL6610A
MOSFET driver controls both high-side and low-side N-
Channel FETs from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t
are provided in the Electrical Specifications. Adaptive shoot-
through circuitry monitors the LGATE voltage and turns on
the upper gate following a short delay time [t
LGATE voltage drops below ~1V. The upper gate drive then
begins to rise [t
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
gate begins to fall [t
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time, t
MOSFET’s gate voltage drops below 1V. The lower gate then
rises [t
prevent both the lower and upper MOSFETs from conducting
simultaneously (shoot-through), while adapting the dead
time to the gate charge characteristics of the MOSFETs
being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower
MOSFET conducts for a longer time during a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement. The 0.4Ω on-resistance
and 4A sink current capability enable the lower gate driver to
PWM
UGATE
LGATE
PDLL
t
PDLL
], the lower gate begins to fall. Typical fall times [t
RL
], turning on the lower MOSFET. These methods
RU
t
] and the upper MOSFET turns on.
PDHU
FU
PDLU
1V
]. The adaptive shoot-through circuitry
t
] is encountered before the upper
RU
PDHL
6
t
PDLU
, after the upper
t
PDHL
PDHU
1V
] after the
FIGURE 1. TIMING DIAGRAM
ISL6610, ISL6610A
2.5V
t
RL
FL
]
t
FL
absorb the current injected into the lower gate through the
drain-to-gate capacitor (C
help prevent shoot through caused by the self turn-on of the
lower MOSFET due to high dV/dt of the switching node.
Tri-State PWM Input
A unique feature of the ISL6610, ISL6610A is the adaptable
tri-state PWM input. Once the PWM signal enters the
shutdown window, either MOSFET previously conducting is
turned off. If the PWM signal remains within the shutdown
window for longer than 80ns of the previously conducting
MOSFET, the output drivers are disabled and both MOSFET
gates are pulled and held low. The shutdown state is
removed when the PWM signal moves outside the shutdown
window. The PWM rising and falling thresholds outlined in
the Electrical Specifications determine when the lower and
upper gates are enabled. During normal operation in a
typical application, the PWM rise and fall times through the
shutdown window should not exceed either output’s turn-off
propagation delay plus the MOSFET gate discharge time to
~1V. Abnormally long PWM signal transition times through
the shutdown window will simply introduce additional dead
time between turn off and turn on of the synchronous
bridge’s MOSFETs. For optimal performance, no more than
100pF parasitic capacitive load should be present on the
PWM line of ISL6610, ISL6610A (assuming an Intersil PWM
controller is used).
Bootstrap Considerations
This driver features an internal bootstrap diode. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. The ISL6610A’s internal
bootstrap resistor is designed to reduce the overcharging of
t
TSSHD
t
PTS
t
RU
t
TSSHD
GD
) of the lower MOSFET and
t
FU
t
PTS
November 22, 2006
FN6395.0