TLE8104E Infineon Technologies, TLE8104E Datasheet - Page 15

• Manufacturer Part Number: TLE8104E
• Description: IC SWITCH LOSIDE 4CH DSO-20
• Manufacturer: Infineon Technologies
• Type: Low Sider

Specifications of TLE8104E

• Input Type: SPI
• Number Of Outputs: 4
• On-state Resistance: 320 mOhm
• Current - Output / Channel: 1A
• Current - Peak Output: 3A
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: DSO-20
• Packages: PG-DSO-20
• Thermal Class: Exposed Pad
• Id Nom: 4 x 1 A
• Pin Count: 20.0 Pins
• Channels: 4.0
• Comment: inductive and resistive loads (e.g. injectors)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000272317; TLE8104E; TLE8104ETR

5.5
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
Figure 10
The SPI protocol is described in
chip is programmed via SPI to enter sleep mode.
5.5.1
CS - Chip Select: The system micro controller selects the TLE8104E by means of the CS pin. Whenever the pin
is in low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are
ignored and SO is forced into a high impedance state.
CS High to Low transition:
•
CS Low to High transition:
•
•
•
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to
for further information.
SO - Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance
state until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to
Data Sheet
The diagnosis information is transferred into the shift register.
Command decoding is only done after the falling edge of CS and a exact multiple (1, 2, 3, …) of eight SCLK
signals have been detected.
Data from shift register is transferred into the input matrix register.
The diagnosis flags are cleared.
SCLK
SO
time
CS
SI
SPI Interface
Serial Peripheral Interface
SPI Signal Description
Section 6
MSB
MSB
for further information.
Section
6
6
6. All registers are reset to default values after power-on reset or if the
5
5
4
4
15
Smart Quad Channel Powertrain Switch
Electrical and Functional Description of Blocks
3
3
CS
. A modulo 8 counter ensures that data is
2
2
1
1
CS
indicates the beginning
LSB
V1.4, 2010-04-26
LSB
TLE8104E
CS
Section 6
. Data is