TLE7184F Infineon Technologies, TLE7184F Datasheet - Page 27
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TLE7184F
Manufacturer Part Number
TLE7184F
Description
IC DRIVER 3PH BRIDGE 48-VQFN
Manufacturer
Infineon Technologies
Datasheet
1.TLE7184F.pdf
(35 pages)
Specifications of TLE7184F
Applications
DC Motor Controller, Brushless (BLDC), 3 Phase
Number Of Outputs
1
Voltage - Supply
6 V ~ 45 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN
Mounting Style
SMD/SMT
Packages
PG-VQFN-48
Operating Range
7.0 - 32.0 V
Iq
50 ?A
Turn On/off Current
-
D.c.-range @ 20khz
0...95%
Numbers Of Integrated Opamps For Load Current Measurement
1.0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Voltage - Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
SP000362096
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TLE7184F
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
The blanking time starts when the dead time is expired and assures that the switch on process of the MOSFET is
not taken into account. It is recommended to keep the switching times of the MOSFETs below the blanking time.
The short circuit detection level is adjustable in an analogue way by the voltage setting at the SCDL pin. There is
a 1:1 translation between the voltage applied to the SCDL pin and the drain-source voltage limit. E.g. to trigger the
SCD circuit at 1 V drain-source voltage, the SCDL pin must be set to 1 V as well. The drain-source voltage limit
can be chosen between 0.3 ... 2 V.
If after the expiration of the blanking time the drain source voltage of the observed MOSFET is still higher then the
SCDL level, the SCD filter time
reaches a specific level (filter time
is removed before the SC is detected, the capacitor is discharged with the same current. The discharging of the
capacitor happens as well when the MOSFET is switched off. It has to be considered that the high side and the
low side output of one phase are working with the same capacitor.
9.2.12
For safety reasons an pull-up resistor at the SCDL pin assures that in case of an open pin the SCDL voltage is
pulled to high levels. In this case an error is set and the IC goes into Error Mode.
9.2.13
The TLE7184F is monitoring the output signal of the operational amplifier. If the output signal reaches a specified
level close to the upper rail (VDD) for a specified time, the System IC detects over current and sets an error signal.
The driver output pulls down the gate-source voltage of all external MOSFETs actively and stays in the Error
Mode.
9.2.14
The TLE7184F has an integrated voltage supply for an external µC. The output current of the supply is limited to
a specified value. This limitation does not cause any error reporting. If the current is limited for a longer time, the
Over Temperature protection will react.
9.2.15
If VS Under Voltage Lock Out is detected or the device is in Sleep Mode, a passive clamping is active as long as
the voltage at VS or VDH is higher than 3V. Even below 3V it is assured that the MOSFET driver stage will not
switch on the MOSFET actively.
The passive clamping means that the BHx and the VREG pin are pulled to GND with specified pull down resistors.
Together with the intrinsic diode of the push stage of the output stages which connect the gate output to BHx
respectively VREG, this assures that the gate of the external MOSFETs are not floating undefined.
9.3
The TLE7184F has a status pin to provide diagnostic feedback to the µC. The logical output of this pin is an open
drain output with integrated pull-down resistor to GND (see
Reset of error registers and Disable
The TLE7184F can be reset by the enable pin RGS. If the RGS pin is pulled to low for a specified minimum time,
the error registers are cleared. If the error is still existing when the RGS pin is pulled to low, no reset will be
performed and the ERR pin stays low. The only exemption of this behavior is the Over Temperature Prewarning.
Even if the junction temperature is exceeding the over temperature prewarning level, the ERR signal goes to high
when RGS is pulled low.
Figure 12
Data Sheet
describes the timing behavior during error reset:
SCDL Pin Open Detection (SCDL_open)
Over Current Shut Down (OCSD)
VDD Current Limitation
Passive Gxx Clamping
ERR Pin
t
SCP
t
SCP
starts to run. A capacitor is charged with a current. If the capacitor voltage
), the error signal is set and the IC goes into Error Mode. If the SCD condition
Description of Modes, Protection and Diagnostic Functions
27
Figure
11).
Rev. 1.0, 2008-12-04
TLE7184F