AT73C237 Atmel, AT73C237 Datasheet
AT73C237
Specifications of AT73C237
Related parts for AT73C237
AT73C237 Summary of contents
Page 1
... An Internal State Machine manages the startup of the other LDOs. An economic High Precision Bandgap (HPBG) provides highly accurate, low noise voltage reference to LDOs while operating in switching mode to optimize the quiescent current. The AT73C237 features a Two-wire Interface (TWI) to increase the efficiency of the system by disabling individually each LDO when not needed. Power ...
Page 2
... Block Diagram Figure 2-1. AT73C237 2 AT73C237 Functional Block Diagram VDD1 (13) LDO1 2.75V/70mA VDD2 (9) LDO2 1.80V/70mA VDD3 (3) LDO3 1.80V/70mA 2.70V Supply Monitor VDD4 (7) LDO4 1.80V/2mA Low Power Bandgap Reference LPBG Main Bandgap LDO Reference HVBG XRESIN (1) XRESO (4) TWI Interface Level Shifters TWCK (11) ...
Page 3
... Input 11 Input 12 Input 13 Output 14 GND/Input 15 Output 16 1. Connect to ground (via an internal pull-down) 2. Connected to VDD1 AT73C237. 3. Connected to VDD1 AT73C237. 4. VDD1 should have the same input voltage. AT73C237 Type Function Digital Reset in pin Analog LDO3 output voltage Power LDO3 input voltage Digital Reset out pin ...
Page 4
... Application Block Diagram Figure 4-1. Typical Application Components Design Schematic Reference D1, D2 AT73C237 4 AT73C237 Application Block Diagram With GPS Module J for 237 C 9 TWI VBG (16) GNDA (15) XRESIN (1) Core and IOs VO3 ( AT73C237 VDD3 ( XRESO (4) VO4 (5) GNDD (6) VDD4 ( Back up Eg: Panasonic Coin-Cell ...
Page 5
... This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. Condition DD1 DD2 DD3 DD4 AT73C237 Min Max Units -40 85 °C 2.8 5 ...
Page 6
... Quiescent Current In Different Operating Modes Table 5-3. Modes MODE0 MODE1 MODE2 AT73C237 6 Quiescent Current In Different Operating Modes Conditions VDD4 not present, chip disabled, all VDDs quiescent current VDD4 present, VDD3 not present (typical mode with back-up battery on VDD4) • LDO4 • ...
Page 7
... LDO1, LDO2, LDO3, and the correct reference voltage and oscillation frequency regulator startup VDD3 voltage is checked. XRESIN. During that state VDD3 voltage is monitored and if lower than 2.6V, LDO regulators 1, 2 and 3 are stopped and XRESO grounded. AT73C237 7 ...
Page 8
... LDO3 en=1 LDO2 en=1 LDO1 en=1 XRESO=1 HPBG en=1 VDD3 Monitor en=1 LDO3 en=1 LDO2 en=1 LDO1 en=1 XRESO=XRESIN AT73C237 8 Startup Procedure VDD4 is present RCOSC Running POR reset signal goes to low Start 100µs (1 clock pulse) Wait xms HPBG Wait 4ms ...
Page 9
... Timing Diagram Figure 7-1. Table 7-1. Parameter t ini ensm t start1 t start2 t resgen t delay 6362A–PMAAC–01-Jul-08 AT73C237 Timings VIN 2.7V VBAT LDO4 POR 1.5V RCOSC t bg HPBG t ini t ensm Supply t ini Monitor enabled t start2 LDO1,2,3 t start1 XRESIN XRESO t resgen Timing Parameters ...
Page 10
... V Total Output Noise NT Table 8-2. LDO1 External Components Schematic Reference C (Input Capacitor (Output Capacitor) 5 AT73C237 10 Comments Switching Regulated Default Programmed With at least 300mV drop out With at least 200mV drop out HiZ output From VDD=3.0V to 3.6V From 10% to 100 From 0 to 100% I ...
Page 11
... LDO1 Output Noise X:1.001 kHz Y:775.467 nVrms 100 uVrms 3 100 nVrms 5Hz AVG: 30 1.605kHz Band:15.4997 uVrms AT73C237 Vin=2.8V Vin=3.3V Vin=5.5V I Load (mA) Vin=2.8V Vin=3.3V Vin=5.5V I Load (mA) A: CH1 Pwr Spec X:1 kHz Y:10.4272 uVrms 100 uVrms LogMag 2 decades ...
Page 12
... V Total Output Noise NT Table 8-4. LDO2 External Components Schematic Reference C (Input Capacitor (Output Capacitor) 6 AT73C237 12 Comments Switching Regulated Default Programmed With at least 300mV drop out With at least 200mV drop out HiZ output From VDD=3.0V to 3.6V From 10% to 100 From 0 to 100% I ...
Page 13
... Y:564.828 nVrms 100 uVrms 3 100 nVrms 5Hz AVG: 30 1.605kHz Band:10.1724 uVrms Vin=2.8V Vin=3.3V Vin=5.5V I Load (mA) Load Regulation: Vout2 = 1.5V Vin=2.8V Vin=5.5V Vin=3.3V I Load (mA) A: CH1 Pwr Spec X:1 kHz 10 uVrms LogMag 1 decades 1 uVrms 1kHz AVG: 30 Band:19.7939 uVrms AT73C237 Y:5.0418 uVrms 103.4kHz 13 ...
Page 14
... OUT V Total Output Noise NT Table 8-6. LDO3 External Components Schematic Reference C (Input Capacitor (Output Capacitor) 7 AT73C237 14 Comments Switching Regulated Default Programmed Programmed With at least 300mV drop out With at least 200mV drop out HiZ output From VDD=3.0V to 3.6V From 10% to 100 From 0 to 100% I ...
Page 15
... AVG: 30 1.605kHz Band:8.7275 uVrms Load Regulation: Vout3 = 1.5V 1.502 1.5005 Vin=3.3V 1.499 1.4975 1.496 1.4945 1.493 1.4915 100 I Load (mA) Vin=2.8V A: CH1 Pwr Spec X:1 kHz 10 uVrms LogMag 1 decades 1 uVrms 1kHz AVG: 30 Band:19.8695 uVrms AT73C237 Vin=2.8V Vin=5.5V Y:4.27822 uVrms 103.4kHz 15 ...
Page 16
... Line regulation static DC ∆V Load regulation static DC Table 8-8. LDO4 External Components Schematic Reference C (Input Capacitor (Output Capacitor) 8 AT73C237 16 Comments Switching Regulated Default HiZ output 2.8V< VDD4 <5.5V 0< I <1.8mA 4 Description 2.2µF ± 15% Ceramic Capacitor, X5R, 0402, 6.3V MURATA: GRM155R60J225ME15 TDK: C1005X5R0J225MT 1µ ...
Page 17
... Factory trimmed encore = dcrun = 0 (1) Not pulsed Pulsed C = 100 100 kHz Description 100 nF ± 15% Ceramic Capacitor, X5R, 0402, 10V MURATA P/N: GRM155R61A104KA01 TDK: C1005X5R1C104KT Conditions Backup Battery or Supercap BAT Conditions AT73C237 Typ Max 3.6 1.231 1 6 300 Min Typ Max 2.8 5 ...
Page 18
... Input supply voltage range I I High input current IH I Low input current IL V High output voltage OH V Low output voltage OL AT73C237 18 Conditions Driven by CPU GPIO Driven by CPU open drain output Connected to V when not used DD4 Conditions Conditions Conditions Limits Min Typ ...
Page 19
... Functional Description The AT73C237 is a fully integrated, attractively priced, combined Power Management. It inte- grates the following power supplies channels. 9.1 LDO1 LDO1 is a 2.75V/70mA LDO, compatible with RF performances. LDO1 can work with supply from 3. 5.5V and needs at least 300 mV of minimum drop-out. This LDO is designed to supply the RF section of wireless devices, showing high PSRR up to 100 kHz with very low noise on wide frequency bandwidth. LDO1 requires a 2.2 µ ...
Page 20
... RF section of wireless devices, showing high PSRR up to 100kHz, very low noise on wide frequency bandwidth. LDO2 requires a 2.2 µF output capacitor. • Additionally, 1.50V output voltages programming is possible via the TWI serial interface. Figure 9-2. AT73C237 20 LDO2 Functional Diagram current reference ...
Page 21
... This LDO is designed to supply RF section of wireless devices, showing high PSRR up to 100 kHz, low noise on wide frequency bandwidth. LDO3 requires a 2.2 µF output capacitor. • Additionally, 1.50V or 1.20V output voltages programming is possible via the TWI serial interface on AT73C237. Figure 9-3. 6362A–PMAAC–01-Jul-08 ...
Page 22
... A Reset Generator produces an output reset (rising from “0” to “1”), called XRESO, at least 100 ms after the input reset state is activated. The input reset state can be produced by: • VDD3 rising up, XRESIN not used or at “1”. • External signal rising up on XRESIN and VDD3 present. AT73C237 22 LDO4 Functional Diagram V ...
Page 23
... Digital Control On AT73C237, the pins TWCK, TWD are respectively the clock and data lines of a true two-wire interface, allowing to activate and disable the output voltage delivered by the regulators LDO1, LDO2, LDO3 and also to change their output voltage value. ...
Page 24
... The interface adds flexibility to the power supply solution, enabling LDO regulators to be con- trolled depending on the instantaneous application requirements. The AT73C237 has the following 7-bit address:1001000. Attempting to read data from register addresses not listed in this section results in 0xFF being read out. ...
Page 25
... TWD S ADDR W • Start • Stop • Write • Read • Acknowledge • Not Acknowledge • ADDR = Device address • IADDR = Internal address 6362A–PMAAC–01-Jul-08 TWD Write Operation S ADDR W A TWD Read Operation A IADDR A S ADDR AT73C237 DATA A IADDR DATA ...
Page 26
... LDO Control: LDO_CTRL (0x00 Table 10-2. Bit 7 10.2 LDO 1,2,3 trim: LDO_TRIM1 (0x08 Table 10-3. Bit 7 2:1 0 AT73C237 26 Registers Register Description LDO_CTRL LDO control LDO_TRIM1 LDO 1,2,3 trim LDO_TRIM4 LDO4 trim LDO_CTRL (0x00) Structure Name Description - Not used Onldo4 ...
Page 27
... Name Description - Not used Sel4 LDO4 output voltage select trcore LDO4 output voltage trimming LDO_TRIM1 (0x08) - Sel4 VO4 1. LDO_TRIM1 (0x08) - trcore VO4 Typ value (1.8V) +80mV -80mV Typ value (1.8V) AT73C237 VO2 Sel3 VO3 1.8V 00 1.8V 1. 1.23V - 11 1 Sel4 ...
Page 28
... Package Information Figure 11-1. Mechanical Package Drawing for 16-lead Quad Flat No Lead Package 6362A–PMAAC–01-Jul-08 AT73C237 29 ...
Page 29
... Ordering Information Table 12-1. Ordering Code AT73C237 AT73C237 30 Ordering Information Package Package Type QFN 3x3 mm Green Temperature Operating Range 0°C to +70°C 6362A–PMAAC–01-Jul-08 ...
Page 30
... Revision History Doc. Rev Comments 6362A First issue 6362A–PMAAC–01-Jul-08 AT73C237 Change Request Ref. 31 ...
Page 31
... LDO2 ...............................................................................................................12 8.3 LDO3 ...............................................................................................................14 8.4 LDO4 ...............................................................................................................16 8.5 High Performance Bandgap (HPBG) ...............................................................17 8.6 Low Power Bandgap (LPBG) ..........................................................................17 8.7 Voltage Monitor ...............................................................................................17 8.8 XRESIN ...........................................................................................................18 8.9 XRESO ............................................................................................................18 8.10 TWCK ..............................................................................................................18 8.11 TWD ................................................................................................................18 9.1 LDO1 ...............................................................................................................19 9.2 LDO2 ...............................................................................................................20 9.3 LDO3 ...............................................................................................................21 9.4 LDO4 ...............................................................................................................22 9.5 High Performance Bandgap (HPBG) ...............................................................22 AT73C237 i ...
Page 32
... Registers ................................................................................................. 26 11 Package Information .............................................................................. 29 12 Ordering Information ............................................................................. 30 13 Revision History ..................................................................................... 31 Table of Contents....................................................................................... i AT73C237 ii 9.6 Low Power Bandgap (LPBG) ..........................................................................22 9.7 Reset Generator ..............................................................................................22 9.8 State Machine ..................................................................................................23 9.9 Oscillator ..........................................................................................................23 9.10 Power-On-Reset ..............................................................................................23 9.11 Supply Monitor .................................................................................................23 9.12 Digital Control ..................................................................................................23 9.13 Two-wire Interface (TWI) Protocol ...................................................................24 10.1 LDO Control: LDO_CTRL (0x00) .....................................................................26 10 ...
Page 33
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...