HCPL-800J-500 Avago Technologies US Inc., HCPL-800J-500 Datasheet - Page 16

• Manufacturer Part Number: HCPL-800J-500
• Description: IC PLC POWERLINE DAA 16-SMD
• Manufacturer: Avago Technologies US Inc.

Specifications of HCPL-800J-500

• Applications: Powerline Data Access
• Current - Supply: 28mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SO-16
• Supply Voltage Range: 4.75V To 5.25V
• Power Dissipation Pd: 1000mW
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 27. An example of a band-pass filter for transmit
Figure 28. LC coupling network
Table 1. Typical component values for band-pass filter and LC
coupling network.
To compensate for the attenuation in the filter, the line
driver stage has 6 dB gain. To prevent the line driver
output from saturating, it is therefore important to
achieve 6 dB of attenuation between Tx-PD-out (pin 13)
and Tx-LD-in (pin 12) either by the inherent filter attenu-
ation or by other means.
16
Filter input
Tx
Rx
Carrier
Frequency (kHz)
110
120
132
150
1µF
R5
Band-Pass Filter
L3 (µH)
680
680
680
680
L2
GND2
L3
GND2
C3 (nF)
3.3
2.7
2.2
1.8
L1
C2
X2
C3
LC Coupling
L2 (µH)
15
10
6.8
6.8
L
N
Filter output
C2 (nF)
150
220
220
220
Transmitter Line Driver
The line driver is capable of driving powerline load im-
pedances with output signals up to 4 V
biasing of the line driver is controlled externally via a
resistor R
biasing point value for modulation frequencies up to
150 kHz is 24 kΩ. For higher frequency operation with
certain modulation schemes, it may be necessary to
reduce the resistor value to enable compliance with in-
ternational regulations.
The output of the line driver is coupled onto the
powerline using a simple LC coupling circuit as shown in
Figure 28. Refer to Table 1 for some typical component
values. Capacitor C2 and inductor L1 attenuate the
50/60 Hz powerline transmission frequency. A suitable
value for L1 can range in value from 200 µH to 1 mH. To
reduce the series coupling impedance at the modulation
frequency, L2 is included to compensate the reactive
impedance of C2. This inductor should be a low resistive
type capable of meeting the peak current requirements.
To meet many regulatory requirements, capacitor C2
needs to be an X2 type. Since these types of capacitors
typically have a very wide tolerance range of 20%, it
is recommended to use as low Q factor as possible for
the L2/C2 combination. Using a high Q coupling circuit
will result in a wide tolerance on the overall coupling
impedance, causing potential communication difficul-
ties with low powerline impedances. Occasionally with
other circuit configurations, a high Q coupling arrange-
ment is recommend, e.g., C2 less than 100 nF. In this case
it is normally used as a compromise to filter out of band
harmonics originating from the line driver. This is not
required with the HCPL-800J.
Although the series coupling impedance is minimized
to reduce insertion loss, it has to be sufficiently large to
limit the peak current to the desired level in the worst
expected powerline load condition. The peak output
current is effectively limited by the total series coupling
resistance, which is made up of the series resistance
of L2, the series resistance of the fuse and any other
resistive element connected in the coupling network.
To reduce power dissipation when not operating in
transmit mode the line driver stage is shut down to a low
power high impedance state by pulling the Tx-en input
(pin 1) to logic low state. The high impedance condition
helps minimize attenuation on received signals.
ref
connected from pin 9 to GND2. The optimum
PP
. The internal