L6740L STMicroelectronics, L6740L Datasheet - Page 19

• Manufacturer Part Number: L6740L
• Description: IC HYBRID CONTROLLERS 48TQFP
• Manufacturer: STMicroelectronics

Specifications of L6740L

• Applications: Hybrid Controllers
• Voltage - Supply: 9 V ~ 15 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Number Of Outputs: 2
• Output Current: 170 A
• Input Voltage: 13.2 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Hybrid Controller: compatible with PVI and SVI CPUs
• Dual Controller: 2 to 4 scalable phases for CPU CORE, 1 phase for NB
• Dual Over-current Protection: Average and per-phase
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L6740L
transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to
L6740L is able to manage individual power OFF for both the sections. The CPU may issue a
serial VID command to power OFF or power ON one section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 7.
Table 8.
1. Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
SVC
SVD
Address phase
Data phase
bits
6:4
6:0
3
2
1
0
7
START
START
SVI communications - send byte
SVI send byte - Address and data phase description
Always 110b.
VID code. See
Not applicable, ignored.
Not applicable, ignored.
CORE section
If set then the following data byte contains the VID code for CORE section.
NB section
If set then the following data byte contains the VID code for NB section.
PSI_L Flag (active low).When asserted, the VR is allowed to enter power-saving
mode. See
BUS DRIVEN BY L6740L
6
Figure
110b
SLAVE ADDRESSING + W
Slave Addressing
5
(1)
(7 Clocks)
Section
7,
.
(1)
Table
Table 8
4
.
5.4.3.
9.
3
and
0
Hybrid CPU support and CPU_TYPE detection
WRITE
Table 9
(1Ck)
Description
(1Ck)
ACK
ACK
ACK
for details about the Set VID command.
BUS DRIVEN BY MASTER (CPU)
DATA PHASE
7
Data Phase
(8 Clocks)
6
0
(1Ck)
ACK
ACK
ACK
STOP
STOP
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