L6740L STMicroelectronics, L6740L Datasheet - Page 39
![IC HYBRID CONTROLLERS 48TQFP](/photos/27/13/271375/tqfp-48_sml.jpg)
L6740L
Manufacturer Part Number
L6740L
Description
IC HYBRID CONTROLLERS 48TQFP
Manufacturer
STMicroelectronics
Datasheet
1.L6740LTR.pdf
(44 pages)
Specifications of L6740L
Applications
Hybrid Controllers
Voltage - Supply
9 V ~ 15 V
Current - Supply
20mA
Operating Temperature
0°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Number Of Outputs
2
Output Current
170 A
Input Voltage
13.2 V
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
0 C
Hybrid Controller
compatible with PVI and SVI CPUs
Dual Controller
2 to 4 scalable phases for CPU CORE, 1 phase for NB
Dual Over-current Protection
Average and per-phase
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Input
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
L6740L
Manufacturer:
ST
Quantity:
20 000
Part Number:
L6740LTR
Manufacturer:
ST
Quantity:
20 000
L6740L
10
LTB Technology™
LTB Technology™ further enhances the performances of dual-edge asynchronous systems
by reducing the system latencies and immediately turning ON all the phases to provide the
correct amount of energy to the load. By properly designing the LTB network as well as the
LTB gain, the undershoot and the ring-back can be minimized also optimizing the output
capacitors count. LTB Technology™ applies only to the CORE section.
LTB Technology™ monitors the output voltage through a dedicated pin detecting Load-
Transients with selected dV/dt, it cancels the interleaved phase-shift, turning-on
simultaneously all phases. it then implements a parallel, independent loop that reacts to
load-transients bypassing E/A latencies.
LTB Technology™ control loop is reported in
Figure 18. LTB Technology™ control loop (CORE section)
The LTB detector is able to detect output load transients by coupling the output voltage
through an R
then compared with the COMP pin level. The resulting duty-cycle programmed is then OR-
ed with the PWMx signal of each phase by-passing the main control loop. All the phases will
then be turned-on together and the EA latencies results bypassed as well.
Sensitivity of the load transient detector and the gain of the LTB Ramp can be programmed
in order to control precisely both the undershoot and the ring-back.
●
Z
F
(s)
Detector design. R
which is desired the controller to be sensitive as follow:
R
COMP
LTB
LTB
=
LTB
dV
----------------- -
25μA
OUT
- C
LT Detect
LTB
FB
network. After detecting a load transient, the LTB Ramp is reset and
Ref
LTB
C
PWM
LTB
- C
LTB Ramp
=
LTB
------------------------------------------------- -
2π N R
DROOP
is design according to the output voltage deviation dV
d V
⋅
COMP
Monitor
⋅
1
VSEN
LTB
⋅
Figure
F
SW
PWM_BOOST
18.
Z
FB
LT Detect
(s)
VID
R
LTB
C
L/N
LTB Technology™
LTB
ESR
C
O
V
OUT
39/44
OUT