ISL62392HRTZ Intersil, ISL62392HRTZ Datasheet - Page 18

• Manufacturer Part Number: ISL62392HRTZ
• Description: IC PWR SUPPLY CONTROLLER 28TQFN
• Manufacturer: Intersil

Specifications of ISL62392HRTZ

• Applications: Power Supply Controller
• Voltage - Supply: 5.5 V ~ 25 V
• Current - Supply: 150µA
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Where:
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as
Equation 26:
Where:
As an example, suppose the high-side MOSFET has a total
gate charge Q
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 18. This layout approach ensures
that the controller does not favor one channel over another
during critical switching decisions. Figure 29 illustrates one
example of how to achieve proper bilateral symmetry.
C
BOOT
- I
- I
- t
- t
- Q
- ΔV
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
inductor current minus 1/2 of the inductor ripple current
current plus 1/2 of the inductor ripple current
saturation
high-side MOSFET
the boot capacitor each time the high-side MOSFET is
switched on
VALLEY
PEAK
ON
OFF
g
BOOT
is the total gate charge required to turn on the
=
is the time required to drive the device into
is the time required to drive the device into cut-off
INDUCTOR
----------------------- -
ΔV
HIGH-SIDE
HIGH-SIDE
MOSFETS
MOSFETS
is the sum of the DC component of the inductor
INDUCTOR
GROUND
, is the maximum allowed voltage decay across
VIAS TO
GROUND
PLANE
VIAS TO
Q
BOOT
is the difference of the DC component of the
g
PLANE
g
, of 25nC at V
PHASE
PHASE
NODE
NODE
VOUT
GND
GND
VIN
VIN
18
GS
OUTPUT
CAPACITORS
OUTPUT
CAPACITORS
= 5V, and a ΔV
ISL62391, ISL62392, ISL62391C, ISL62392C
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
BOOT
(EQ. 26)
of
Signal Ground and Power Ground
The bottom of the ISL62391, ISL62392, ISL62391C and
ISL62392C TQFN package is the signal ground (GND)
terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL62391, ISL62392, ISL62391C and
ISL62392C to the island of ground plane under the top layer
using several vias for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors, and the source of the lower MOSFETs to the
power ground plane.
PGND (Pin 19)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 17)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 4)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 18)
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pin, preferably on
the same side of the PCB as the ISL62391, ISL62392,
ISL62391C and ISL62392C ICs.
EN (Pins 11 and 24), and PGOOD (Pin 1)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 10 and 25) and ISEN (Pins 9 and 26)
For DCR current sensing, the current-sense network,
consisting of R
the inductor pads for accurate measurement. Connect
LINE OF SYMMETRY
PIN 4 (VCC)
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
FIGURE 30. SYMMETRIC LAYOUT GUIDE
OCSET
ISL6239
and C
PIN 18 (PVCC)
SEN
, needs to be connected to
C o
C o
L2
L1
Ci
Ci
L2
L1
U2
U1
April 7, 2011
FN6666.5