SE97BTP,547 NXP Semiconductors, SE97BTP,547 Datasheet - Page 34

• Manufacturer Part Number: SE97BTP,547
• Description: IC TEMP SENSOR DIMM 8HWSON
• Manufacturer: NXP Semiconductors

Specifications of SE97BTP,547

• Package / Case: 8-WSON (Exposed Pad), 8-HWSON
• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Temperature Threshold: + 150 C
• Full Temp Accuracy: 2 C
• Digital Output - Bus Interface: I2C
• Digital Output - Number Of Bits: 11 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Description/function: Temperature Sensor
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5055-2

NXP Semiconductors
Table 28.
[1]
[2]
[3]
SE97B_1
Product data sheet
Disable
Timeout
0
1
0
1
X
SMBus Time-out.
0 — enabled (default)
1 — disabled
Shutdown time-out.
0 — SMBus Time-out disabled when SHMD = 1
1 — SMBus Time-out enabled when SHMD = 1 (default)
Thermal Sensor Shutdown mode.
0 — active (default)
1 — shutdown
[1]
SMBus register setting guide
Enable
SDTO
X
X
1
1
0
[2]
SHMD
[3]
0
0
1
1
1
Table 27.
[1]
[2]
Bit
1
0
When the part comes out of shutdown, the state of the EVENT pin will not change until after the first
temperature conversion. When the part enters shutdown, the ACT (TEMP[15]), AAW (TEMP[14]) and BAW
(TEMP[13]) bits (flip-flops) will be cleared.
The STTS424E02 allows clearing the interrupt when in comparator mode, but the other competitors do not.
Thermal sensor
behavior
TS is active and
SMBus TO is on
TS is active and
SMBus TO is off
TS is disabled and
SMBus TO is on
TS is disabled and
SMBus TO is off
TS is disabled and
SMBus TO is off
Symbol
RFU
DisableARA
SMBus Time-out register bit description
Rev. 01 — 27 January 2010
Description
reserved; always ‘0’
Disable SMBus Alert Response Address (ARA).
When either of the Critical Trip or Alarm Window lock bits is set, this bit
cannot be altered until unlocked.
0 — SMBus ARA is enabled
1 — disable SMBus ARA (default)
SPD behavior
SPD read/write and
SMBus TO is on
SPD read/write and
SMBus TO is off
SPD read/write and
SMBus TO is on
SPD low power
read/write and
SMBus TO is off
SPD low power
read-only and
SMBus TO is off
DDR memory module temp sensor with integrated SPD
Power mode
Full power,
oscillator is running
Full power,
oscillator is running
Lower power,
oscillator is off unless
bus active or write to
SPD
Lower power,
oscillator is off unless
write to the SPD
Lowest power,
oscillator is off all
the time
…continued
Use
JEDEC - SMBus for
TS and SPD
(like SE97 if TS is on)
I
TO
JEDEC - SMBus for
TS and SPD
I
TO
I
TO (like SE97 if TS is
off)
2
2
2
C-bus - no SMBus
C-bus - no SMBus
C-bus - no SMBus
© NXP B.V. 2010. All rights reserved.
SE97B
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