ADT7463ARQZ ON Semiconductor, ADT7463ARQZ Datasheet - Page 31

• Manufacturer Part Number: ADT7463ARQZ
• Description: IC REMOTE THERMAL CTRLR 24-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7463ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

By reading the PWMx current duty cycle registers, users can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode.
OPERATING FROM 3.3 V STANDBY
The ADT7463 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5
states, the core voltage of the processor is lowered in these states.
If using the dynamic T
the processor would change the CPU temperature and change
the dynamics of the system under dynamic T
wise, when monitoring THERM, the THERM timer should
be disabled during these states.
DYNAMIC T
<1> V
When the power is supplied from 3.3 V STBY and the V
voltage drops below the V
Once the core voltage, V
thing gets re-enabled and the system resumes normal operation.
REV. C
• Status Bit 1 (V
• SMBALERT gets generated if enabled.
• THERM monitoring is disabled. The THERM timer
• Dynamic T
• The ADT7463 is prevented from entering the shutdown
should hold its value prior to the S3 or S5 state.
from being adjusted due to an S3 or S5 state.
state.
Figure 38. Control PWM Duty Cycle Manually with
a Resolution of 0.39%
CCP
LO = 1
MIN
MIN
CONTROL REGISTER 1 (REG. 0x36)
CCP
control is disabled. This prevents T
MIN
) in Status Register 1 gets set.
CCP
CCP
, goes above the V
mode, lowering the core voltage of
low limit, the following occurs:
CYCLE WITH 8-BIT
VARY PWM DUTY
RESOLUTION
MIN
CCP
control. Like-
low limit, every-
Rev. 4 | Page 31 of 52 | www.onsemi.com
CCP
MIN
–31–
Note that since other voltages can drop or be turned off during
a low power state, these voltage channels set status bits or
generate SMBALERTs. It is still necessary to mask out these
channels prior to entering a low power state using the interrupt
mask registers. When exiting the low power state, the mask bits
can be cleared. This prevents the device from generating
unwanted SMBALERTs during the low power state.
XOR TREE TEST MODE
The ADT7463 includes an XOR Tree Test Mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XOR Tree, it is
possible to detect opens or shorts on the system board. Figure 39
shows the signals that are exercised in the XOR Tree Test Mode.
The XOR Tree Test is invoked by setting Bit 0 (XEN) of the
XOR Tree Test Enable Register (Reg. 0x6F).
POWER-ON DEFAULT
The ADT7463 does not monitor temperature and fan speed by
default on power-up. Monitoring of temperature and fan speed
is enabled by setting the Start Bit in Configuration Register 1
(Bit 0, Address 0×40) to 1. The fans run at full speed on power-
up. This is because the BHVR bits (Bits 7:5) in the PWMx
configuration registers are set to 100 (fans run full speed) by default.
Figure 39. XOR Tree Test
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
VID0
VID1
VID2
VID3
VID4
PWM1/XTO
ADT7463