ISL6439CB Intersil, ISL6439CB Datasheet - Page 12

• Manufacturer Part Number: ISL6439CB
• Description: IC CNTRLR PWM SYNC BUCK 14-SOIC
• Manufacturer: Intersil

Specifications of ISL6439CB

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 325kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 5 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Frequency-max: 325kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6439 requires two N-Channel power MOSFETs.
These should be selected based upon r
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see equations on next
page). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6439
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low V
through protection present aboard the ISL6439 may be
circumvented by these MOSFETs if they have large parasitic
impedences and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Losses while Sinking current
Losses while Sourcing current
P
P
P
P
LOWER
UPPER
UPPER
LOWER
Where: D is the duty cycle = V
= Io
= Io
=
=
t
f
SW
s
Io
2
Io
is the switching frequency.
2
2
x r
x r
2
is the combined switch ON and OFF time, and
×
×
DS(ON)
DS(ON)
r
r
DS ON
DS ON
GS(ON)
(
(
x D
x (1 - D)
)
)
×
×
D
characteristics. The shoot-
12
(
1 D
+
–
SW
1
-- - Io
2
OUT
⋅
)
which increases the
+
/ V
×
1
-- - Io
2
V
⋅
IN
DS(ON)
IN
,
×
×
V
t
SW
IN
, gate supply
×
×
t
f
SW
s
ISL6439, ISL6439A
×
f
s
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, C
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
the boot diode drop, V
Q
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
where Q
MOSFET, C
the bootstrap voltage immediately before turn-on, and
V
The bootstrap capacitor begins its refresh cycle when the gate
drive begins to turn-off the upper MOSFET. A refresh cycle
ends when the upper MOSFET is turned on again, which
varies depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the Equation 10 and solving for C
Typical gate charge values for MOSFETs considered in
these types of applications range from 20nC to 100nC.
Since the voltage drop across Q
V
Q
C
BOOT2
BOOT1
LOWER
BOOT
GATE
+
-
ISL6439
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
=
GATE
=
is the bootstrap voltage immediately after turn-on.
is simply V
.
C
---------------------------------------------------- -
V
BOOT
BOOT1
BOOT
BOOT
is the maximum total gate charge of the upper
Q
BOOT
GND
GATE
×
is the bootstrap capacitance, V
–
UGATE
PHASE
(
CPVOUT
BOOT
LGATE
CPVOUT
D
conducts, to a voltage of CPVOUT less
V
V
BOOT
BOOT1
BOOT2
D
, develops a floating supply voltage
, plus the voltage rise across
C
+
-
V
BOOT
–
- V
D
V
BOOT2
D
LOWER
. A schottky diode is
Q
Q
V
UPPER
LOWER
IN
)
is negligible,
NOTE:
V
NOTE:
V
G-S
BOOT
G-S
November 5, 2008
= V
BOOT1
= V
.
CC
(EQ. 10)
CC
(EQ. 11)
FN9057.5
-V
is
D