ISL6535CRZ-T Intersil, ISL6535CRZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL6535CRZ-T
• Description: IC CTRLR SYNC BUCK PWM 16-QFN
• Manufacturer: Intersil

Specifications of ISL6535CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 100%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

therefore, dependent upon the value of the soft-start
capacitor, C
soft-start capacitance value can be calculated through
Equation 3:
If an external reference is used, then the soft start
capacitance can be calculated through Equation 4:
Prebiased Load Startup
Drivers are held in tri-state (UG pulled to Phase, LG pulled to
PGND) at the beginning of a soft-start cycle until two PWM
pulses are detected. The low side MOSFET is turned on first
to provide for charging of the bootstrap capacitor. This method
of driver activation provides support for start-up into prebiased
loads by not activating the drivers until the control loop has
entered its linear region, thereby substantially reducing output
transients that would otherwise occur had the drivers been
activated at the beginning of the soft-start cycle.
SSDONE
Soft-start done is only available in the 16 Ld QFN packaging
option of the ISL6535. When the soft-start pin reaches 4V, an
open drain signal is provided to support sequencing
requirements. SSDONE is deasserted by disabling of the part,
including pulling SS low, and by POR and OCP events.
Oscillator
The oscillator is a triangular waveform, providing for leading
and falling edge modulation. The peak to peak of the ramp
amplitude is set at 1.9V and varies as a function of
frequency. At 50kHz the peak to peak amplitude is
approximately 1.8V while at 1.5MHz it is approximately 2.2V.
In the event the regulator operates at 100% duty cycle for 64
clock cycles an automatic boot cap refresh circuit will
activate turning on LG for approximately 1/2 of a clock cycle.
C
C
SS
SS
=
=
30μA t
----------------------------
30μA t
----------------------------
V
FIGURE 3. TYPICAL SOFT-START INTERVAL
REFEXT
2V
SS
⋅
⋅
V
. If the internal reference is used, then the
SS
SS
EN
7
t
SS
V
OUT
V
SS
(EQ. 3)
(EQ. 4)
ISL6535
Overcurrent Protection
The OCP function is enabled with the drivers at start-up.
OCP is implemented via a resistor (R
capacitor (C
drain of the high side MOSEFT. An internal 200
source develops a voltage across R
compared with the voltage developed across the high side
MOSFET at turn-on as measured at the PHASE pin. When
the voltage drop across the MOSFET exceeds the voltage
drop across the resistor, a sourcing OCP event occurs.
C
voltage across R
on the input bus.
A 120ns blanking period is used to reduce the current
sampling error due to leading-edge switching noise. An
additional simultaneous 120ns low pass filter is used to
further reduce measurement error due to noise.
OCP faults cause the regulator to disable (upper and lower
drives disabled, SSDONE pulled low, soft-start capacitor
discharged) itself for a fixed period of time, after which a
normal soft-start sequence is initiated. If the voltage on the
SS pin is already at 4V and an OCP is detected, a 30mA
current sink is immediately applied to the SS pin. If an OCP
is detected during soft-start, the 30
applied until the voltage on the SS pin has reached 4V. This
current sink discharges the C
Once the voltage on the SS pin has reached approximately
0V, the normal soft-start sequence is initiated. If the fault is
still present on the subsequent restart, the ISL6535 will
repeat this process in a hiccup mode. Figure 4 shows a
typical reaction to a repeated overcurrent condition that
places the regulator in a hiccup mode. If the regulator is
repeatedly tripping overcurrent, the hiccup period can be
approximated by Equation 5:
t
I
OCP
HICCUP
OCSET
FIGURE 4. TYPICAL OVERCURRENT PROTECTION
V
SS
is placed in parallel with R
=
I
LOAD
8V C
----------------------- -
OCSET
30μA
⋅
OCSET
SS
) connecting the OCSET pin and the
t
HICCUP
in the presence of switching noise
SS
capacitor in a linear fashion.
V
SSDONE
µ
OCSET
A current sink will not be
OCSET
OCSET
, which is then
to smooth the
) and a
µ
A current
May 5, 2008
FN9255.1
(EQ. 5)