ISL6740AIVZA-T Intersil, ISL6740AIVZA-T Datasheet - Page 10

• Manufacturer Part Number: ISL6740AIVZA-T
• Description: IC CTRLR PWM DBL-ENDED 16-TSSOP
• Manufacturer: Intersil

Specifications of ISL6740AIVZA-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 16 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-TSSOP
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

protection, bidirectional synchronization, fault indication, and
adjustable frequency.
Oscillator
The ISL6740A has an oscillator with a programmable
frequency range to 2MHz, and can be programmed with two
resistors and a capacitor. The use of three timing elements,
R
setting the oscillator frequency.
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by R
determined by R
where T
respectively, T
is the oscillator frequency. One output switching cycle
requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation
delays of approximately 10ns/transition. This delay ads
directly to the switching duration, but also causes overshoot
of the timing capacitor peak and valley voltage thresholds,
effectively increasing the peak-to-peak voltage on the timing
capacitor. Additionally, if very low charge and discharge
currents are used, there will be increased error due to the
input impedance at the C
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
FIGs. 3 and 4 graphically portray the deadtime and oscillator
frequency as function of the timing components.
Implementing Synchronization
The oscillator can be synchronized to an external clock
applied to the SYNC pin or by connecting the SYNC pins of
multiple ICs together. If an external master clock signal is
used, the free running frequency of the oscillator should be
~10% slower than the desired synchronous frequency. The
external master clock signal should have a pulse width
greater than 20ns. The SYNC circuitry will not respond to an
external signal during the first 60% of the oscillator switching
cycle.
T
T
T
D
DT
TC
C
D
SW
=
≈
≈
, R
=
0.5 R
0.02 R
----------- -
T
=
T
SW
TD
1 D
C
C
T
–
•
C
, and C
•
and T
+
TC
TD
T
D
SW
•
•
D
C
TC
TD
=
T
C
T
are the charge and discharge times,
is the oscillator free running period, and f
allows great flexibility and precision when
----------- -
F
T
and C
and C
SW
1
S
S
T
T
T
. The discharge duration is
.
pin.
S
10
(EQ. 2)
(EQ. 3)
(EQ. 4)
(EQ. 5)
(EQ. 6)
ISL6740A
The SYNC input is edge triggered and its duration does not
affect oscillator operation. However, the deadtime is affected
by the SYNC frequency. A higher frequency signal applied to
the SYNC input will shorten the deadtime. The shortened
deadtime is the result of the timing capacitor charge cycle
being prematurely terminated by the external SYNC pulse.
Consequently, the timing capacitor is not fully charged when
the discharge cycle begins. This effect is only a concern
when an external master clock is used, or if units with
different operating frequencies are paralleled.
Soft-Start Operation
Soft-start is controlled using an external capacitor in
conjunction with an internal current source. Soft-start
reduces stresses and surge currents during start up.
Upon start up, the soft-start circuitry clamps the error voltage
input (V
start voltage. The soft-start clamp does not actually clamp
the error voltage input as is done in many implementations.
Rather the PWM comparator has two inverting inputs such
that the lower voltage is in control.
The output pulse width increases as the soft-start capacitor
voltage increases. This has the effect of increasing the duty
cycle from zero to the regulation pulse width during the soft-
start period. When the soft-start voltage exceeds the error
voltage at the PWM comparator inputs, soft-start is
completed. Soft-start occurs during start-up, after recovery
from a Fault condition or overcurrent/short circuit shutdown.
The soft-start voltage is clamped to 4.5V.
The Fault signal output is high impedance during the soft-
start cycle unless an active fault (see Fault Conditions) is
present. A pull-up resistor to VREF or a pull-down resistor to
ground should be added to achieve the desired state of Fault
during soft-start.
Gate Drive
The outputs are capable of sourcing and sinking 0.5A peak
current, but are primarily intended to be used in conjunction
with a MOSFET driver due to the 5V drive level. To limit the
peak current through the IC, an external resistor may be
placed between the totem-pole output of the IC (OUTA or
OUTB pin) and the gate of the MOSFET. This small series
resistor also damps any oscillations caused by the resonant
tank formed by the parasitic inductances in the traces of the
board and the device’s input capacitance.
Undervoltage Monitor, Inhibit, and Feed Forward
The UV/FF input is used for input source undervoltage
lockout and inhibit functions as well as sensing the input
voltage for feed forward compensation.
If the node voltage falls below 1.00V, a UV shutdown fault
occurs. This may be caused by low source voltage or by
intentional grounding of the pin to disable the outputs. There
is a nominal 10µA switched current source used to create
hysteresis. The current source is active only during a
ERROR
pin) indirectly to a value equal to the soft-
February 7, 2005
FN9195.0