ISL6560CBZ-T Intersil, ISL6560CBZ-T Datasheet - Page 10

• Manufacturer Part Number: ISL6560CBZ-T
• Description: IC CORE VOLTAGE REG PWM 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6560CBZ-T

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 50%
• Voltage - Supply: 3 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To calculate the dissipation in the 5mΩ resistor, we used
only half of the ripple current, 4A, to give a nominal
dissipation of:
Where I
10mΩ, 1W resistors in parallel were selected.
R
As discussed in the section under Droop Voltage and shown
in Figure 1, resistor R
transconductance error amplifier. It is this resistor that sets
the droop voltage or regulation. Like any feedback system,
the higher the gain the better the regulation. The value of this
resistor may be determined from the following equation:
The ni term is the ratio of the V
comparator threshold voltage; see Figure 2. R
of two resistors that form a voltage divider from the internal
3V reference supply.
As described earlier in the Circuit Description section, the
output voltage of the gm amplifier establishes the threshold
voltage of the current comparator. At approximately 1V, the
current comparator threshold voltage is near zero. With no
current demands, the regulator output voltage would be the
same as the programmed DAC voltage. However, an 8A
ripple current was selected for this design. This results in the
output of the gm amplifier moving upwards to supply the
ripple current. The voltage at the COMP pin, V
The voltage divider establishes the reference voltage for
V
amplifier must drive the COMP pin 50mV more positive to
bring it to 1.25V from the 1.2V originally set. This additional
50mV output will result in an input voltage to the error
amplifier of: 50mv / 19.1 = 2.62mV below the programmed
DAC voltage of 1.8V. Neglected, is a negative term
associated with the 60ns delay of the current comparator.
This delay will cause the current ramp to be slightly greater
than predicted by the equation. This means that the initial
setting should be slightly reduced to account for the increase
in current.
COMP
L
V
∴
∴ gm Amplifier Gain =
R
Selection
SET
Power
Power
L
gmAmplifierGain
=
P
that was set to 1.2V for this design, so the error
=
---------------------------------------- -
gm R
=
is the peak current and D is the duty cycle. Two
ni R
1V
1V
=
=
×
×
Ip
0.69W per channel or 1.38W for both channels
+
+
2
SENSE
I
OUT
I
--------------------------------------------------------------- -
RMS
RIPPLE
8A
---------------------------------------------
×
D
×
×
×
5mΩ
=
L
2
R
=
establishes the gain of the
2
SENSE
Ip D
=
×
gm
R
2
------------------------------------------------------- -
2.2mS
×
SENSE
×
12.5
10
RL
=
12.5
=
COMP
Ip
3
×
=
=
0.4
×
1.63mΩ
×
2.2mS
1V
1.8V
------------
12V
ni
5mΩ
2
to the current
+
×
250mV
0.15
×
×
8.7k
·
2
×
L
5mΩ
=
SET
=
is made up
=
8.7kΩ
19.1
1.25V
, will be:
ISL6560
Once the value for R
that make up the voltage divider must be determined. Figure
8 shows the equations to determine the resistor network that
makes up R
C
Optimum transient response depends upon the selection of
the compensation capacitor network placed across the
output of the transconductance error amplifier.
To a first order, the selection of the capacitor, C
across the error amplifier may be determined by making the
product of the regulator output resistance and output
capacitors equal to the product of the R
the equation for the compensation capacitor:
A 1nF capacitor was selected from transient testing. To
prevent excessive phase shift due to the compensation
capacitor, it is usually necessary to place a resistor inseries
with the capacitor to prevent excessive phase shift beyond
the frequency of interest. This is pole cancellation and the
resistor is approximately 0.5 x R
network and the equivalent circuit is approximately 0.5 x R
Many variables have been used in the selection of the
various gain and filter networks to this point. A broad range
of component tolerances range from
been used in the design. Therefore, it is important to
evaluate the entire system with dynamic pulse load testing.
This will verify optimum transient response and also indicate
poor response in terms of excessive overshoot, ringing or
oscillation if the compensation network is not optimum.
C
C
C
and R
FIGURE 8. EQUATIONS TO DETERMINE R
=
R
-------------------------------------- -
V
OUT
REF = 3V
C
L
FIGURE 9. COMPENSATION CIRCUIT
C
.
R
Selection
R
C
R
×
L
U
B
C
R
R
V
R
OUT
this voltage is V
B
B
REF = 3V
V
C
=
To COMP pin,
=
SET
L
------------------------------------
V
-----------------------------
3V 1.25V
RU
R
=
is set, only the values of the resistors
REF
To COMP pin
B
R
1.25V
=
1.63mΩ
---------------------------------------- -
V
–
U
SET
1V
=
–
V
--------------- -
1.25V
8.7k
+
SET
SET
3V
R
I
--------------------------------------------------------------- -
U
RIPPLE
×
×
L
AC Equivalent
C
. Figure 9 shows this
20.9k
||
×
9mF
R
C
×
R
C
R
8.7k
B
= 0.5 x R
R
U
±
R
1% to
=
U
C
L
×
=
=
=
R
and C
R
=
2
1.68nF
14.9k
R
L
SENSE
V
-------------- -
V
20.9k
L
REF
SET
L
±
L
20% have
C
DIVIDER
C
. This yields
×
, placed
×
R
ni
L
FN9011.3
L
.