ISL6560CBZ-T Intersil, ISL6560CBZ-T Datasheet - Page 12

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ISL6560CBZ-T

Manufacturer Part Number
ISL6560CBZ-T
Description
IC CORE VOLTAGE REG PWM 16-SOIC
Manufacturer
Intersil
Datasheet

Specifications of ISL6560CBZ-T

Pwm Type
Current Mode
Number Of Outputs
1
Frequency - Max
2MHz
Duty Cycle
50%
Voltage - Supply
3 V ~ 12 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
0°C ~ 70°C
Package / Case
16-SOIC (3.9mm Width)
Frequency-max
2MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage Sampling
2. Current sense is critical, especially at lower current levels
3. The lines to the current sense resistor should be parallel
4. Place the current sense filter network near the controller.
5. Make sure the DC plus pulse voltage inputs to the current
1. To obtain optimum regulation use the Kelvin connection
where the current comparator threshold voltage is lower.
A good Kelvin connection requires that the voltage
sample must be taken at the R
not at the planes to which the resistor is connected.
and run away from the PHASE or PWM signals to prevent
coupling of spikes to the current comparator input that
may delay or advance triggering of the comparator.
Parallel routing will work towards equal exposure for both
lines, so that the comparator common mode rejection
characteristic will reduce the influence of coupled noise.
This will help reduce extraneous inputs to the comparator.
sense comparator, CS+ and CS-, do not exceed the
voltage on the VCC pin by more than the specified limit of
VCC + 0.3V.
for the input voltage sample as shown in Figure 11. The
ground connection, Pin 9 of the ISL6560 should be
connected to the system ground at the load.
12V
VID Codes
Processor
+V
FIGURE 11. SCHEMATIC DIAGRAM SHOWING ONLY ONE CHANNEL OF ‘IDEAL’ COMPONENT PLACEMENT
Input
from
IN
{
{
Next to IC
1
2
3
4
5
6
7
8
Locate
Parts
VID4
VID3
VID2
VID1
VID0
COMP
FB
CT
12
ISL6560
PWRGD
SENSE
PWM1
PWM2
GND
VCC
REF
CS+
CS-
16
15
14
13
12
11
10
9
resistor ends, and
Locate
Parts
Next
to IC
ISL6560
Keep Leads Together
& Away from Output
1
2
3
4
UGATE
BOOT
PWM
GND
HIP6601ECB
Other Considerations
2. The two voltage sampling lines described in item 1 above
1. Keep the leads to the timing capacitor connected to pin
2. When using a transistor to disable the converter by
3. As in all designs, keep decoupling networks near the pins
4. Large power and ground planes are critical to keeping
should also be routed away from any high-current or high-
pulse voltages such as the phase lines or pads. Doing
this will reduce the possibility of coupling undesired
pulses into the feedback signal and either modifying the
output of the error amplifier or, if of sufficient amplitude,
spuriously triggering the current comparator by
readjusting the threshold voltage.
CT short and return the ground directly to Pin 9.
pulling the CT pin to ground, place the transistor close to
the CT pin to minimize extraneous signal pickup.
that must be decoupled. For example, the
decoupling/filter network on the FB input. The series
resistor should be located next to the FB pin.
performance and efficiency high. Consider a 1mΩ
resistance in a 40A supply line. With 1.8V output, this
results in slightly over 2% power loss in the 72W supply.
PHASE
LGATE
PVCC
VCC
8
7
6
5
Try to return bypass
capacitors to ground
of lower MOSFETs
Place Near Drains of the
Output Transistors
+V
CORE
FN9011.3

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