ISL6244CR Intersil, ISL6244CR Datasheet - Page 19

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
FIGURE 25. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6244 CIRCUIT
R
C
-------------------
2π LC
C
C
V
1
+
-
DROOP
=
=
R
C
R
----------------------------------- -
2πV
>
FB
C
FB
0.75V
2
f
0
PP
C
2πf
----------------------------------- -
(OPTIONAL)
, has already been chosen as
C
0.75V
R
19
0
C
IN
FB
V
pp
and C
f
0
COMP
IN
VDIFF
IOUT
LC
FB
C
.
0
. The target
0
ISL6244
.
Case 3:
In Equations 24, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V
the peak-to-peak sawtooth signal amplitude as described in
Figure 16 and Electrical Specifications.
Once selected, the compensation values in Equations 24
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equations 24 unless some performance issue is noted.
The optional capacitor C
noise away from the PWM comparator (see Figure 25). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Case 2:
FIGURE 26. COMPENSATION CIRCUIT FOR ISL6244 BASED
C
will not need adjustment. Keep the value of C
C
R
1
1
C
while observing the transient performance on an
CONVERTER WITHOUT LOAD-LINE
REGULATION
R
C
-------------------
2π LC
f
R
C
C
C
0
R
C
C
1
>
FB
R
=
=
----------------------------- -
2πC ESR
=
=
C
R
------------------------------------------------------------ -
(
2π
R
0.75V
------------------------------------------------ -
C
≤
FB
2
2πV
2
2
FB
f
(
, is sometimes needed to bypass
, and be prepared to install a high-
)
1
C
0
V
--------------------------------------------
2
C
<
PP
----------------------------------------- -
0.75 V
f
PP
0
IN
----------------------------- -
2πC ESR
0.75V
2
0.75 V
2π f
(
)
V
R
(
2π
ESR
PP
FB
(
COMP
1
0
IN
VDIFF
)
IN
2
IOUT
R
V
f
0
IN
(
f
FB
pp
) C
FB
0
ESR
2
C
L
)
L
LC
. Slowly increase the
LC
)
December 28, 2004
C
from
(EQ. 24)
PP
FN9106.3
is